The physics of the memories that store bits in electron spin and atomic polarization rather than trapped charge: how magnetic tunnel junctions, spin-transfer and spin-orbit torque, racetrack domain walls, and ferroelectric switching actually work, what they promise on endurance and latency, the honest 2026 production reality at Everspin and Avalanche, and where storage-class memory really sits in the hierarchy.
Semiconductors
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Spintronics and the Memory After NAND -
Chiplets and Advanced Packaging: When the Die Stopped Scaling Why monolithic dies stopped scaling and the industry moved to multi-die designs glued together by interposers and bridges. The yield math that forces the issue, the 2.5D/3D vocabulary, AMD Infinity Fabric versus Intel Foveros and EMIB versus Apple UltraFusion versus TSMC CoWoS, and the honest reality of where chiplets pay off and where they just add cost.
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HBM4 and the Memory Wall for AI Why every modern AI accelerator is pin-limited on bandwidth rather than starved for math, how High Bandwidth Memory actually works, what each generation from HBM2 to HBM4 buys, why LLM inference is a memory problem in disguise, and the three-company supply story that makes HBM the real binding constraint on AI economics.
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Failure Analysis: From RMA to Root Cause A working tour of the semiconductor failure-analysis toolkit: how a returned unit becomes a localized defect and then a corrective action. From curve tracing and emission microscopy through FIB cross-sections and SEM imaging, with the discipline of non-destructive-before-destructive that keeps you from destroying your only evidence.
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How a Wafer Fab Works A wafer fab is the most complex factory humanity builds: a few core unit processes run as a loop hundreds of times to print a billion transistors on a disc of silicon. A first-principles tour of litho, etch, dep, implant, and CMP; cleanroom logistics; the three-month, thousand-step cycle; and why a leading-edge fab costs north of twenty billion dollars.
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How Semiconductors Are Tested A chip is not finished when it leaves the fab — it is finished when test decides it can be sold. This is the full flow from wafer sort through final test, burn-in, and adaptive screening, plus the brutal economics that make test time a line item on every unit's bill of materials.
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Semiconductor Yield Engineering Yield, not transistor density, decides who wins a process node. A first- principles tour of defect-density yield models, why memory is the most forgiving product in silicon, the economics of binning, and how the yield ramp over a node's life is the real driver of cost and competitiveness.
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The NAND Commodity Cycle Why NAND flash is a commodity whose price crashes and spikes with terrifying violence: the multi-year capex lead times, fixed-cost economics, and brutal consolidation down to five players that turn storage into a boom-bust market where the cycle, not the engineering, decides who lives and who dies.
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3D NAND Architecture: Building Memory Sideways, Then Up Why planar NAND hit a wall at 15nm, how the industry turned the bit line vertical, charge-trap versus floating-gate cells, string stacking, the channel-hole etch that gates everything, CMOS under and bonded to the array, and what the 300-layer class actually means.
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Chip Export Controls: Why You Can't Buy an H100 in Shanghai How US export controls turned the AI compute supply chain into a theater of geopolitics: the TPP and performance-density thresholds, the A800/H800 workaround, ASML's EUV monopoly as the real chokepoint, China's domestic scramble, and why the rules keep flip-flopping under your feet.
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NAND Trim: Calibrating Flash Memory at the Factory Every NAND die leaves the fab analog and imperfect. Trim is the layer of per-die calibration constants — read levels, program voltages, pump regulation, timing — that makes billions of slightly different devices behave like one uniform product. From first principles to what managing trim settings actually involves.
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QLC, PLC, and the Density Endgame Each extra bit per cell doubles the voltage states crammed into the same window: the exponential-pain, linear-gain math of multi-level NAND, where QLC genuinely works versus where it's a trap, SLC caching as the universal apology, and an honest read on whether PLC ever ships.
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Solar PV: From Photon to Inverter The semiconductor physics of free energy: how the photovoltaic effect works at the PN junction, why Shockley-Queisser caps single-junction silicon near 30%, what's actually inside a panel and how it degrades, MPPT as a hill-climbing algorithm, string inverters versus microinverters honestly compared, the duck curve solar inflicts on the grid, and real payback math for a homelab-scale install.
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The Read Window Budget: Margin Accounting in NAND Design Every NAND reliability mechanism — retention loss, read disturb, cycling wear, temperature shift — is a withdrawal from one shared account: the read window budget. How the budget is defined, measured, allocated, and defended, and why every flash failure story is ultimately a budget overrun.
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What Comes After NAND? Every "NAND killer" so far has died instead: the 3D XPoint post-mortem, honest assessments of MRAM, ReRAM, FeRAM, and PCM, why incumbency in memory is nearly unbeatable, and where the post-NAND future actually lives — bonded silicon, CXL tiers, and NAND replacing NAND.
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How a Transistor Actually Works: From Sand to Switch The physics under every computing device, from semiconductor doping and the depletion region through MOSFETs and CMOS, to the leakage crises that drove FinFETs, GAAFETs, and the relentless geometry of Moore's Law.
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How Chips Are Actually Fabbed: From Ingot to Package Semiconductor fabrication is the most capital-intensive manufacturing process humanity has ever devised: five hundred process steps, wavelengths of light shorter than a bacterium's cell wall, and a single fab that costs more than a nuclear aircraft carrier. Here is how it actually works.
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Bell Labs and the Transistor: The Lab That Built the Modern World How a regulated telephone monopoly funded the most productive industrial lab in history, why the transistor was invented twice in six weeks by people who hated each other, and how an antitrust decree turned New Jersey physics into Silicon Valley.