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QLC, PLC, and the Density Endgame

9 min read The Physics of Computing
nand-flashstorageqlchardwaresemiconductors
Contents

There are two ways to make a NAND die hold more data: build more cells, or make each cell hold more bits. The first path — 3D stacking — costs etch and deposition. The second path costs nothing physical at all: the cell that stores two voltage states can, with sufficient nerve, store sixteen. No new layers, no new fab tools, just firmware, trims, and audacity. That free lunch is why bits-per-cell has crept relentlessly upward — SLC, MLC, TLC, QLC, with PLC perpetually auditioning — and the catch is one of the cleanest asymmetries in engineering: the gain is linear and the pain is exponential. Each added bit increases capacity by a shrinking fraction while doubling the number of states squeezed into a voltage window that does not grow. QLC is the current frontier of that bargain, PLC is its speculative edge, and understanding exactly where the math bites is the difference between deploying QLC where it shines and discovering its weaknesses in production.

The Arithmetic of Audacity

A cell storing n bits needs 2^n distinguishable threshold-voltage states, hence 2^n − 1 valleys between them, all inside the same usable Vt window (the budget mechanics are in the NAND read-window budget post):

            states   valleys   capacity gain      avg valley width
                               vs previous        vs previous
  SLC   1     2         1           —                  —
  MLC   2     4         3         +100%            ~ 1/3
  TLC   3     8         7         +50%             ~ 3/7
  QLC   4    16        15         +33%             ~ 7/15
  PLC   5    32        31         +25%             ~ 15/31

  Gain per added bit:   1/n      -> shrinking linearly
  States per added bit: 2^n      -> doubling every step

  And the electron budget makes it worse: if a cell's full
  window spans ~N storable electrons, the charge separating
  adjacent QLC states is ~N/15, PLC ~N/31. In a modern cell
  that is a few dozen electrons per state boundary —
  retention loss of a handful of electrons is now a
  meaningful fraction of a state.

The table’s last column understates the damage, because valleys don’t just need to exist at time zero — they need to survive retention slump, disturb, cycling widening, and cross-temperature shift for the warranty period. Every one of those consumers takes a roughly fixed-millivolt bite, so halving the valley width more than halves the surviving margin. This is why each bits-per-cell step has demanded a disproportionate escalation in supporting machinery: finer ISPP programming steps and more verify levels (slower programming), more read levels per page (slower reads), stronger soft-decision LDPC (more silicon, worse tail latency), and continuous read-level tracking by the controller (mandatory, not optional, for QLC).

The pain shows up in every operational number. Moving TLC→QLC, program time roughly doubles per bit of progress made, sustained write bandwidth drops, read latency rises with the extra sensing levels, and rated endurance falls from the few-thousand-cycle class to the ~1,000–1,500 class (vendor- and generation-dependent; enterprise QLC with aggressive overprovisioning claims more). Retention behavior tightens correspondingly — fewer electrons per state means the same physical leakage moves you further through the margin.

Why Bother: The Economics

A 33% density gain looks weak next to a layer-count generation — until you notice it’s nearly free and multiplicative. The same 300-layer array sells as 33% more terabytes by changing the operating mode, and array cost dominates die cost. At fleet scale the arithmetic is brutal and decisive: a hyperscaler buying exabytes cares about $/TB and TB/rack-unit, and QLC wins both. This is why QLC adoption was led not by bargain consumer SSDs but by the largest enterprise drives — the 61TB and now 122TB-class QLC monsters from Solidigm and peers that let an object-storage rack replace an aisle (the 3D NAND architecture post covers why the physical scaling that would otherwise deliver those terabytes keeps getting harder).

The fine print engineers should actually read:

  • The density gain is array-level, not system-level. QLC needs more ECC parity, more overprovisioning for its worse write amplification, and more spare blocks for its shorter endurance. The shipped $/TB advantage over TLC is real but consistently smaller than 33%, and in some generations it has been embarrassingly thin.
  • Same die, different personality. Several designs run TLC or QLC modes on identical silicon; “QLC” is then a firmware-and-trim decision made at product definition, which tells you how much of multi-level NAND is calibration and ECC rather than cell design (the NAND trim post describes that machinery).
  • Endurance ratings are workload-shaped. QLC endurance specs lean on sequential, large-block write assumptions (JEDEC enterprise workloads weight differently). A QLC drive rated in DWPD under sequential fill behaves very differently under sustained 4K random writes — not because the spec lies, but because write amplification multiplies physical cycles per host byte.

SLC Caching: The Universal Apology

Every consumer QLC (and most TLC) drive hides its program-speed problem behind a pseudo-SLC cache: a region of the array temporarily operated at one bit per cell — fast to program, enormous margins — that absorbs incoming writes and destages to QLC in the background.

  host writes -->  [ pSLC cache ]  --(background fold)-->  [ QLC ]

  cache state      apparent drive speed
  -----------      --------------------
  empty            NVMe-fast (SLC program speed)
  filling          still fast
  exhausted        CLIFF: host now waits on QLC folding;
                   sustained writes can drop below a
                   hard disk's sequential rate on the
                   worst drives

The mechanics worth knowing: dynamic caches borrow free user-space blocks (cache size shrinks as the drive fills — the cliff moves closer exactly when you have the least room to maneuver), folding consumes endurance (data is written twice: once as pSLC, once as QLC), and benchmark numbers are nearly always cache numbers. The cliff is not a defect; it’s the visible edge of the TLC/QLC speed gap, relocated to where reviewers hopefully won’t sustain writes long enough to find it. For homelab and fleet purposes alike, the only honest QLC write benchmark is a sustained fill past cache exhaustion at realistic fullness — the same “test the steady state, not the demo” discipline that applies to any storage claim (the ZFS homelab storage post).

Where QLC genuinely works, none of this matters: read-heavy and read-mostly workloads (content serving, object storage, AI training-data reservoirs, archival tiers with occasional large sequential ingest) never stress program speed or endurance, and QLC reads are only modestly slower than TLC. Where it’s a trap: write-intensive databases, ZFS SLOG/metadata duty, scratch space, anything that sustains small random writes. The deployment rule is one sentence — QLC is priced like cold-ish storage because physically it is cold-ish storage — and most QLC disappointment is someone ignoring that sentence.

PLC: The Perpetual Two Years Away

Five bits per cell — 32 states, 31 valleys — has been demonstrated for years (Kioxia showed PLC operation publicly back in 2021; every vendor has internal demos) and shipped by no one at scale. The math explains the gap between demo and product. The capacity gain is +25%, the smallest step yet. The valley width is roughly half of QLC’s, which was already living on tracked read levels and soft-decision decoding. The supporting cast needed — near-continuous calibration, heavy soft reads, possibly per-block adaptive bit modes — eats latency, controller silicon, and power that all count against that 25%.

The credible paths to shippable PLC are themselves telling:

  • Constrained operating envelopes: PLC only for cold, sequential, append-mostly data, with the drive silently running hotter regions at fewer bits — turning bits-per-cell into a per-block policy rather than a product spec.
  • A better cell first: PLC riding on a future architecture step (new trap-layer materials or geometry) that widens the window or tightens distributions — i.e., PLC as a beneficiary of the next physics improvement rather than a standalone trick.
  • Exotic conditions: SK hynix and academic work on low-temperature operation shows beautifully tight distributions at cryogenic temperatures; barring datacenters refrigerating storage shelves, this remains a research curiosity, though it neatly demonstrates that the obstacle is thermal physics, not cleverness.

A reasonable position as of this writing: QLC took roughly a decade from demo to mainstream, PLC’s gain is smaller and its physics is harder, and the competing route to cheap cold bits (more layers, bonded peripheries, and possibly HDD-and-tape simply refusing to die) keeps the bar high. PLC will likely ship eventually, in the constrained-envelope form, and “eventually” has missed every predicted date so far. Beyond PLC, the per-cell road visibly ends — 6 bits would need 63 valleys for a +20% gain — which is one reason the industry’s longer-term attention shifts to different physics entirely (what comes after NAND).

Reading a Multi-Level Product Like an Engineer

A short field guide for evaluating any QLC (and someday PLC) product:

Question Why it matters
Sustained write rate after cache exhaustion, at 80% full? The only write number that predicts production behavior
Endurance rating under what workload assumption? DWPD under JESD219 sequential-weighted ≠ your random-write reality
What does p99.99 read latency look like aged vs fresh? Tail latency is where thin valleys and soft-decision retries surface first
Power-off retention at rated endurance? Fewer electrons per state = the spec that quietly tightened
Dynamic or static pSLC cache, and how big when full? Determines where the cliff is and whether you’ll ever see it
Per-workload TCO vs TLC at shipped $/TB? The 33% array gain shrinks after parity, OP, and spares

Verdict

Multi-level NAND is the cheapest density lever the industry has ever had, and it behaves exactly like its arithmetic: linear gain, exponential pain, with each step viable only because trims, tracking, and LDPC absorb what the physics gave up. QLC has crossed from gamble to workhorse — but as a placed workhorse, superb in read-mostly and large-sequential roles and miserable when treated as general-purpose TLC with a discount sticker. The pSLC cache is an apology, not a cure; benchmark past it or be benchmarked by production. PLC remains the roadmap item that proves the endgame is near: a 25% prize guarded by 31 valleys, shippable only in constrained envelopes, and chronically two years away. For newcomers, the one idea to keep is that bits-per-cell is not a feature toggle but a renegotiation of every margin in the device. For practitioners: insist on aged, cache-exhausted, workload-matched numbers, because in multi-level NAND, the datasheet describes the honeymoon and the ledger describes the marriage.

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