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What Comes After NAND?

8 min read The Physics of Computing
storagehardwaresemiconductorsemerging-memorynand-flash
Contents

The graveyard of NAND killers is now large enough to draw conclusions from. Over two decades, a procession of technologies arrived with credible physics, real silicon, and confident roadmaps — and every one of them is either dead, retreated into an embedded niche, or still “two generations from volume.” The most instructive corpse is Intel and Micron’s 3D XPoint: a genuinely superior memory by most physical measures, backed by two giants, productized for seven years, and killed anyway. Its failure was not physics. It was a precise demonstration of why the question “what replaces NAND?” is mostly malformed — because in memory markets, better doesn’t beat cheaper-and-good-enough, and nothing on Earth is cheaper per bit than NAND while NAND keeps improving. This post does the post-mortem properly, assesses each surviving candidate without vendor optimism, and ends where the evidence points: the post-NAND future is mostly NAND, rearranged.

The Incumbency Math

Understand the defender before scoring the challengers. NAND’s position rests on three compounding facts:

Cost per bit without peer. 3D NAND ships hundreds of layers with 4 bits per cell (the 3D NAND architecture post and the QLC/PLC density endgame post cover both levers). Any challenger starts against a target of fractions of a cent per gigabyte — and the target moves down every year.

Amortized everything. Five major manufacturers, decades of process learning, qualified controllers and firmware stacks, JEDEC standards, and fabs whose capex is already sunk into an ecosystem that knows exactly how to absorb the next generation. A new memory needs not just a cell but this entire stack, from scratch, while losing money per bit for years. The challenger must survive its unprofitable adolescence inside a commodity market famous for brutal price cycles.

A tolerable weakness profile. NAND is slow, wears out, and can’t be byte-addressed — and the industry has spent twenty years building software that doesn’t care: FTLs, log-structured filesystems, caches, tiering. Every workaround that makes NAND livable also shrinks the value of a challenger whose pitch is “no workarounds needed.”

The structural consequence: a new memory cannot win by being better at NAND’s job. It must find a job NAND cannot do at all, survive there, and hope the niche grows. Every realistic candidate below is best understood through that lens.

3D XPoint: The Canonical Post-Mortem

What it was: a phase-change memory (chalcogenite cells switched between crystalline and amorphous resistance states) in a crosspoint array with an ovonic threshold switch as selector — byte-addressable-ish, persistent, no erase blocks, endurance orders of magnitude beyond NAND, latency far below it. Launched 2015 with the famous “1000x” slideware; shipped as Optane SSDs (~10μs class latency, against ~80–100μs for NAND NVMe) and, more interestingly, as Optane Persistent Memory DIMMs (~100–350ns — memory-bus persistent storage).

It was real, it worked, and Intel killed it in 2022, taking a half-billion-plus inventory writedown on the way out; Micron had exited and sold the Lehi fab earlier the same year. The autopsy findings generalize:

  • It landed between two stools. Faster than NAND but ~3–5x its cost per bit; cheaper than DRAM but slower. Every workload analysis ended the same way: buy more DRAM, or buy more NAND, or buy a cache layer of one in front of the other. The tier in between was real but thin.
  • The economics never compounded. NAND rode layer scaling and QLC downward in cost while XPoint, low-volume in a single fab, barely moved. The gap widened over its product life. A memory that doesn’t ride a steep learning curve loses to one that does, regardless of starting elegance.
  • The killer app needed someone else’s software. Persistent memory’s real value demanded applications rewritten for byte-addressable durability (PMDK, DAX filesystems). The rewrite asked the whole industry to invest in a single-vendor memory with uncertain future — a chicken-and-egg that never hatched.
  • One ecosystem, one exit. Proprietary interface (DIMM mode required Intel CPUs with specific memory controllers) meant the addressable market was a subset of a subset. When Intel’s enthusiasm cooled, there was no second source to carry it.

The lesson is not “PCM is bad” — PCM persists today in embedded and automotive roles. The lesson is that a memory product is a learning curve plus an ecosystem, and XPoint had neither.

The Survivors, Honestly Scored

Technology Mechanism Genuine strength Fatal flaw (for NAND’s job) Realistic role
STT/SOT-MRAM Magnetic tunnel junction resistance Speed, effectively unlimited endurance, radiation-hard Cell size and cost; density ceilings far below NAND Replacing embedded NOR/SRAM in MCUs; caches; aerospace
ReRAM Conductive filament in an oxide Simple cell, low power, analog states Filament stochasticity — variability that fights multi-level operation Embedded NVM at logic nodes; analog in-memory AI accelerators
PCM Crystalline/amorphous resistance Proven at scale (XPoint), fast writes Drift, reset power, and the demonstrated economics above Embedded/automotive; selector-based crosspoints if costs ever close
FeRAM / FeFET (HfO2) Ferroelectric polarization The research darling: fast, low-power, CMOS-friendly hafnia Endurance/retention trade still unsolved at density; young The one to actually watch; embedded first, density later if ever
NOR flash The old guard Code execution in place, byte reads Density hopeless Boot and firmware storage, forever
DNA / glass / holographic Molecular or optical archival Density and longevity beyond all silicon Write cost and speed, by factors of thousands Archival research; check back in a decade

Two threads deserve emphasis. Hafnium-oxide ferroelectrics are the most credible long-shot: ferroelectricity in HfO2 (discovered ~2011) means a persistent, fast, low-power cell made of a material already in every fab — the first emerging memory whose materials story is boring, which is high praise. The open problems (endurance of the polarization switching, retention-vs-endurance trade, 3D integration) are real but moving. ReRAM’s analog second life matters too: arrays of resistive cells used not as storage but as in-place multiply-accumulate fabric for neural network inference — a job NAND genuinely cannot do, which by incumbency math is exactly the kind of beachhead that survives (the transistor explainer gives the device-physics grounding for why analog conductance states make multiplication nearly free).

Where the Future Actually Went

While the NAND-killer candidates fought physics, the actual post-NAND architecture arrived from two unglamorous directions:

CXL ate persistent memory’s job. The dream XPoint died chasing — a capacity tier between DRAM and flash — got rebuilt in software and interconnect instead of exotic materials. Compute Express Link puts pools of ordinary DRAM (and eventually anything) behind a cache-coherent fabric: tiered, pooled, hot-pluggable memory, with the OS doing page-temperature migration. The tier exists; it’s just made of commodity parts. That is the XPoint lesson applied: when a job can be done by rearranging cheap incumbents, that beats inventing a new device.

The roadmap money went vertical and sideways. NAND’s own future is bonded silicon — array wafers fused to separately-optimized logic wafers (the 3D NAND architecture deep dive) — and the profit future of memory companies went to HBM, where DRAM die stack with logic for the AI build-out. Both point the same direction: the next decade of memory progress is packaging, bonding, and heterogeneous stacking more than new storage physics. Storage-side, the same story: hundreds more layers, smarter host interfaces (zoned namespaces, flexible data placement), and density per package via 16-high die stacks.

And the cold end refuses to die. HDDs (with HAMR finally shipping) and tape keep absorbing the archival exabytes at costs flash can’t touch, which removes the one market where an exotic ultra-dense memory might have undercut NAND from below (the post on how data lives on platters and flash covers why magnetic recording still has road left).

So the honest answer to the title: what comes after NAND is NAND — charge storage on vertical strings, more layers, more bits, bonded to better logic, fronted by smarter interfaces — for any horizon you can plan against. The interesting changes arrive around it: CXL reshaping the memory hierarchy above, analog in-memory compute carving a new category beside, ferroelectrics maturing in embedded niches below, and packaging dissolving the boundary between memory and logic.

Verdict

Betting against NAND has been the worst trade in semiconductors for twenty years, and the reasons are structural, not sentimental: an unmatched learning curve, a fully amortized ecosystem, and weaknesses the software world long ago routed around. 3D XPoint is the controlled experiment that proved it — superior physics, two giants, seven years, dead — and its lesson generalizes to every candidate in the table: in memory, economics is the physics that matters. For an engineer calibrating expectations: treat every “NAND replacement” announcement as an embedded-niche announcement until it demonstrates a cost curve, not a cell; watch hafnia ferroelectrics as the genuine dark horse; take CXL seriously as the thing that actually changed the hierarchy; and assume your storage roadmap for the next decade is layers, bits, and bonding. The post-NAND era will arrive eventually — no incumbency is forever — but it will arrive the way 3D NAND itself did: not as a better product slotting into the old socket, but as a different economics finding a dimension nobody else was using.

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