How a Transistor Actually Works: From Sand to Switch

June 10, 2026 17 min read The Physics of Computing

hardwaresemiconductorsphysicscpueda

Contents

Every line of software you have ever written runs because a voltage on a thin sliver of silicon can coax a river of electrons into existence or snuff it out in picoseconds. The transistor is not a curiosity of hardware engineers; it is the physical substrate of every abstraction in computing, from logical AND to a large language model. Understanding how it works — really works, not “it’s like a switch” — removes the magic from things that otherwise feel arbitrary: why smaller is faster, why smaller also leaks, why CMOS came to dominate, why fabs are now building structures smaller than a flu virus. The history starts with semiconductor physics, not with silicon specifically, and that distinction matters.

Semiconductors and the band gap

A conductor — copper, aluminum — has electrons in its outer shell that are barely bound to their atoms. At room temperature they move freely, and current flows with little resistance. An insulator — glass, diamond — has outer electrons locked tightly in valence bonds; you have to apply enormous electric fields to dislodge any of them. A semiconductor sits between these extremes in a way that turns out to be enormously useful: its resistance is high at low temperatures, low at high temperatures, and — critically — tunable with impurities.

The explanation lives in band theory. Electrons in a solid can occupy energy ranges called bands. The valence band is the highest range that is fully occupied at absolute zero. The conduction band is the next one up, normally empty. The gap between them is the band gap, measured in electron-volts. In copper the gap is zero — bands overlap. In diamond it is 5.5 eV — practically unreachable at room temperature. Silicon’s gap is 1.12 eV. Germanium’s is 0.67 eV.

The band gap is why silicon won over germanium, and the choice was not obvious for the first decade of transistor work. Germanium was what Shockley, Bardeen, and Brattain used in 1947 (covered in detail in the Bell Labs transistor history), and it has a real advantage: lower band gap means electrons can be excited into the conduction band more easily, which yields higher carrier mobility and faster devices at a given geometry. But that same lower band gap becomes a liability at elevated temperature. At roughly 70 °C, germanium’s intrinsic carrier concentration rises enough to swamp any deliberate doping; the transistor stops working as designed. Military and automotive applications made this a fatal flaw. Silicon’s 1.12 eV band gap keeps intrinsic carriers negligible to well past 150 °C. Silicon also forms a chemically stable native oxide — SiO2 — that adheres perfectly to the silicon surface, acts as a high-quality electrical insulator, and is straightforwardly grown by heating silicon in oxygen. Germanium’s native oxide, GeO2, is water-soluble and mechanically fragile. When Jack Kilby at TI and Robert Noyce at Fairchild developed the planar process in 1958–59, silicon’s native oxide was the detail that made photolithography on a flat surface tractable. Germanium never recovered commercially.

Property	Silicon (Si)	Germanium (Ge)
Band gap (eV)	1.12	0.67
Electron mobility (cm²/V·s)	1,400	3,900
Hole mobility (cm²/V·s)	450	1,900
Max junction temp (°C)	~150	~70
Native oxide	SiO2 (stable, insulating)	GeO2 (water-soluble)
Abundance in Earth’s crust	28% (second most)	trace

Higher carrier mobility is germanium’s enduring advantage; modern high-performance nodes use silicon-germanium alloy (SiGe) in strained channels precisely to recover that mobility while keeping the silicon base. But the substrate you start with is silicon, and the oxide that gates the transistor is still primarily SiO2 or a derivative high-k dielectric — silicon’s original gift.

Doping: writing a charge map into silicon

Pure crystalline silicon is a lousy conductor. Each silicon atom forms four covalent bonds with its neighbors in a diamond cubic lattice. At room temperature a handful of electrons will have enough thermal energy to jump to the conduction band, leaving behind positively-charged vacancies called holes. This intrinsic concentration is around 1.5 × 10^10 carriers per cubic centimeter — vanishingly small compared to the 5 × 10^22 silicon atoms per cubic centimeter in the lattice.

Doping introduces foreign atoms at concentrations of 10^15 to 10^20 per cubic centimeter — one impurity per million to one per hundred silicon atoms.

N-type doping uses Group V elements: phosphorus, arsenic, antimony. Each has five valence electrons; four form bonds, and the fifth is only weakly bound (~0.05 eV, vs 1.12 eV to cross the gap). At room temperature virtually every donor atom is ionized, leaving a free electron in the conduction band. Majority carriers are electrons, hence n-type.

P-type doping uses Group III elements: boron, gallium, indium. Each has three valence electrons. The missing bond is readily filled by a neighbor’s electron, creating a mobile hole — a positively-charged vacancy. Majority carriers are holes, hence p-type.

The net charge of either region is zero — ionized dopant atoms and mobile carriers balance. The available mobile carrier concentration is orders of magnitude above intrinsic silicon, and that difference is what devices exploit.

The PN junction and depletion region

Bring a p-type region and an n-type region into contact — either by doping adjacent zones of the same crystal or by implanting one type into the surface of the other — and something interesting happens at the interface before any voltage is applied.

Electrons from the n-side diffuse toward the p-side (where their concentration is low). Holes from the p-side diffuse toward the n-side. As electrons and holes meet they recombine and annihilate. This leaves behind the fixed, ionized dopant atoms that donated or accepted them: positive ions on the n-side, negative ions on the p-side. The region emptied of mobile carriers is the depletion region.

Those fixed charges create an electric field pointing from n to p — opposing further diffusion. Equilibrium is reached when the drift of carriers in the electric field exactly cancels the diffusion. The result is a built-in potential across the depletion region: about 0.6–0.7 V for silicon, less for germanium.

Apply a forward bias (positive terminal to p-side): it opposes the built-in field, narrows the depletion region, and above ~0.6 V current flows — electrons pour from n to p, holes from p to n. Apply a reverse bias (positive to n-side): the field widens the depletion region and only a tiny minority-carrier leakage flows. This asymmetry is a diode. The PN junction is the fundamental building block of every transistor type; how the depletion region responds to voltage determines the speed and switching characteristics of every device built from it.

The BJT: the historical stepping stone

The bipolar junction transistor (BJT) was the first commercially practical transistor, developed from Shockley’s junction transistor theory in 1951. It arranges two PN junctions back to back: either n-p-n or p-n-p, with three regions called emitter, base, and collector.

In an NPN BJT, the emitter is heavily doped n-type; the base is lightly doped p-type and very thin (micrometers); the collector is moderately doped n-type. With no base current, a thick depletion region blocks the collector-emitter path. Inject a small base current — forward-bias the emitter-base junction — and minority carriers (electrons) flood into the thin base. Because the base is so thin that most electrons cross it before recombining, they reach the collector junction and are swept through. A small base current controls a large collector current: the transistor amplifies with a current gain β typically between 50 and 500.

BJTs are still used where their properties matter: RF amplifiers, analog circuits, high-voltage switching. But they carry a fundamental cost: base current must flow continuously to hold the device on. In logic gates, this static power becomes prohibitive as gate count rises.

Parameter	BJT	MOSFET
Control mechanism	Base current	Gate voltage
Input impedance	Low (kΩ range)	Very high (GΩ range)
Static power (conducting state)	Non-zero (IB × VBE)	Near zero (no gate current)
Speed (at discrete scale)	Very fast (ECL < 1 ns)	Comparable at deep submicron
Integration density	Limited (base current routing)	Excellent
Sensitivity to temperature	Moderate	Lower
Dominant use today	RF, analog, high-voltage	Digital logic, memory

The BJT’s fundamental limitation for digital logic is that input impedance. Driving the base of a BJT requires current from the previous stage, which means each gate has a fan-out limit and power consumption that does not scale down with voltage. The MOSFET solves this.

The MOSFET: voltage controls current without current flowing through the gate

The Metal-Oxide-Semiconductor Field-Effect Transistor is the device that actually runs the digital world. Its structure is simple to describe and subtle to understand.

             Gate (metal or polysilicon)
                |
     ___________v___________
    |     Gate Oxide (SiO2) |
    |_______________________|
    |  Source |  Channel  | Drain |
    |  (n+)   |    (p)    | (n+)  |
    |_________|___________|_______|
                   p-type substrate (body)

In an NMOS transistor, source and drain are heavily doped n-type regions implanted into a p-type substrate. Between them lies the channel — the p-type substrate surface directly beneath the gate. The gate is separated from the silicon by a thin insulating layer of SiO2 (or a modern high-k dielectric). No DC current flows through the gate. The gate is electrically isolated.

Apply a positive voltage to the gate. The electric field from the gate penetrates the oxide and into the silicon beneath. It repels holes (majority carriers in the p-type substrate) away from the surface, leaving behind the fixed negative ions of the acceptor dopants — a depletion region just beneath the gate. Increase the voltage further. Eventually the field is strong enough to attract minority carriers — electrons — to the surface from the n+ source and drain regions. When the electron concentration at the surface equals the hole concentration in the bulk, you have reached the threshold voltage, Vt. Increase the gate voltage above Vt and a thin sheet of electrons forms at the surface: the inversion layer, or channel.

This conducting channel connects source to drain. Electrons flow from source to drain when drain voltage is applied; current flows. The gate voltage modulates the channel’s charge density — its conductance. More gate voltage, more electrons in the channel, lower resistance, more current. Below threshold, the inversion layer doesn’t form, the channel is absent, and current is negligible.

The key property is that the gate is insulated. No steady-state current flows into the gate. The input impedance of a MOSFET gate is in the gigaohm range. A MOSFET gate that is charged to a given voltage holds that voltage indefinitely (limited only by leakage through the thin oxide) and draws no current from the driving stage. A CMOS inverter’s output can drive thousands of gate inputs, limited only by the capacitance that must be charged and discharged — not by current gain limits as in a BJT.

PMOS transistors are the complement: source and drain are p-type, channel is formed in an n-type body, and the gate must be driven negative relative to source to form an inversion layer of holes. PMOS is intrinsically slower than NMOS because hole mobility in silicon is about one-third of electron mobility.

CMOS: eliminating static power

Complementary MOS pairs one NMOS and one PMOS in a circuit topology that, in its ideal form, consumes zero static power. The canonical example is the inverter.

        VDD
         |
        [PMOS] <-- Gate (input)
         |
         +-----> Output
         |
        [NMOS] <-- Gate (input)
         |
        GND

Input LOW: PMOS gate is low, PMOS is ON; NMOS is OFF. Output is pulled HIGH through PMOS. No path from VDD to GND — no static current. Input HIGH: NMOS is ON, PMOS is OFF, output pulled LOW. Again no VDD-to-GND path.

During transitions both devices are briefly partially ON and a switching-current pulse flows: P = α × C × VDD² × f, where α is the fraction of gates switching and C is total switched capacitance. Static power in ideal CMOS is zero.

Before CMOS, NMOS logic (the 8080, the 6502) used a pull-up transistor permanently connected to VDD; that path dissipated current whenever the output was LOW. A 1972-era NMOS gate burned milliwatts of static power; CMOS burned microwatts. At 2,300 transistors this was tolerable; at a million it was not. CMOS dominated by the late 1980s not because it was faster — it wasn’t initially — but because it was the only technology that could scale gate count without burning the die.

Why smaller transistors are faster — and leakier

The most consequential equation in semiconductor engineering is not Ohm’s law; it is the expression for switching delay in a MOSFET:

t_delay ∝ (C_load × V_DD) / I_drive

The drive current I_drive scales with channel width and inversely with channel length. Shorter channel means higher drive current for the same gate width — the electric field across the channel is steeper, carriers transit faster. Smaller transistors also have smaller parasitic capacitances: the gate area is smaller, reducing gate capacitance; the junction areas shrink, reducing source/drain capacitances. The supply voltage can also scale down, reducing the energy per switch as V² in the dynamic power formula. Every dimension that shrinks makes the transistor faster, cooler per switch, and smaller — more of them per unit area. This is the physics behind Moore’s Law.

But smaller transistors have problems that larger ones do not.

Short-channel effects. When the channel length approaches the depth of the source/drain depletion regions, those regions start to “share” control of the channel with the gate — the source and drain steal some of the electrostatic control from the gate. The threshold voltage drops and becomes sensitive to drain voltage (DIBL — drain-induced barrier lowering). The gate can no longer fully turn the transistor off.

Quantum tunneling through the gate oxide. The gate oxide thickness has scaled roughly in proportion to channel length, following the scaling rules that keep the electric field in the channel constant. At the 90 nm node (early 2000s), Intel’s gate oxide was about 1.2 nm thick — roughly 5 atoms of SiO2. At those dimensions, electrons tunnel through the oxide quantum mechanically; gate leakage current appears even when the transistor is nominally off. This leakage is exponential in oxide thickness. Halving the oxide thickness increases gate tunneling current by several orders of magnitude.

Subthreshold leakage. Even below the threshold voltage, some current flows. The channel doesn’t switch off like a digital step; the inversion layer thins exponentially with gate voltage according to the subthreshold slope, limited by thermodynamics to about 60 mV/decade at room temperature. This means a transistor that is “off” at 0 V but designed to turn on at 0.7 V still leaks a current that is 10^(700/60) = 10^11.7 times smaller than the on-current — which sounds large but becomes a serious problem when a billion transistors are all slightly leaking simultaneously and the ratio of on-current to leakage current is too small to provide reliable logic margins.

By the 65–45 nm nodes, leakage power was consuming as much of the power budget as switching power. Static power scaling was broken. The answer required a structural change to the transistor.

FinFET and GAAFET: wrapping the gate around the channel

The conventional planar MOSFET controls the channel from one side only — from above, through the gate oxide on the top surface. As channel length shrinks, this single-sided control loses to the three-dimensional electrostatics of short-channel effects. The solution is to give the gate more surfaces to exert control from.

FinFET (Fin Field-Effect Transistor) was introduced at the 22 nm node by Intel in 2011 (Intel called it Tri-Gate). The channel is a narrow, vertical fin of silicon rising above the substrate. The gate wraps around three sides of the fin — top and both sidewalls. This tripled gate contact improves electrostatic control dramatically: the gate can turn the channel fully off even with a short channel length, because it controls the fin from three sides and there is less volume for the drain field to “reach around” the gate and lower the source potential barrier.

          Gate
         _____
        |     |
    ____|     |____
   |    | Fin |    |
   |    |_____|    |
   | Source  Drain |
   |_______________|
         Substrate

The fin width must itself be tightly controlled — wider fins are harder for the gate to control from the sides. At modern nodes, fin widths are in the 5–7 nm range. FinFETs reduced subthreshold leakage by roughly 10x compared to planar devices at the same channel length and improved drive current per unit footprint. The dynamic power advantage of smaller transistors was restored, and static power came back under control.

GAAFET (Gate-All-Around FET), introduced at Samsung’s 3GAE process node in 2022 and at TSMC’s 2 nm node, wraps the gate entirely around the channel on all four sides. The channel material is a stack of nanosheets or nanowires — horizontal ribbons of silicon suspended in the gate stack, with gate oxide on all surfaces. This geometry provides maximum electrostatic control: the gate sees the channel from all directions, and the current flows horizontally through each nanosheet while the gate wraps around the outside.

The transition from planar to FinFET to GAAFET is a story of geometry compensating for physics. Each time the electrostatics of scaling broke the transistor’s off-state control, engineers added another surface for the gate to act on. The underlying physics of the inversion layer, threshold voltage, and field-effect modulation is the same; the architecture wrapped around it is increasingly three-dimensional.

From one transistor to a billion-gate die

The planar process, developed by Noyce and Fairchild in 1959–60, established the enabling insight: all transistors on a chip could be fabricated simultaneously by selectively doping and depositing materials on a flat silicon wafer, using photolithography to define patterns. Modern chips stack 10–15 layers of metal interconnect over the device layer, each patterned to route the signals between billions of switches. CMOS, as described above, removed static power as the limiting factor in integration density; the combination of planar process and CMOS drove gate counts from the 4004’s 2,300 transistors in 1971 to tens of billions on a 300 mm wafer today.

The RISC-vs-CISC era — explored in how the RISC-vs-CISC war ended in a tie — was a debate about how to exploit that density: complex instructions or simple pipelines. The transistor physics was neutral, but power constraints of dense CMOS pushed architects toward simpler logic with shorter cycle times. Modern BIOS/UEFI firmware, described in the BIOS/UEFI deep dive, runs during the first moments a transistor-dense SoC is powered; every rail-sequencing constraint in that firmware exists because the billions of switches underneath it were built with doping profiles and oxide thicknesses calibrated to exact voltage ranges.

Verdict

The transistor is not an engineering accident. It is the necessary consequence of band gap physics, carrier statistics, and electrostatic field control. Silicon won because 1.12 eV sits at the sweet spot of room-temperature stability, native oxide quality, and lattice purity. The MOSFET’s insulated gate made CMOS possible, and CMOS made billion-transistor dies economically viable by eliminating static power. Scaling made each switch faster and cheaper by reducing charge and channel transit time, and scaling broke each generation’s assumptions about leakage, forcing FinFETs and then GAAFETs as geometric answers to electrostatic problems.

The honest trade-offs are these: smaller channels are faster but harder to control; thinner gate oxides increase capacitive coupling but invite quantum tunneling; lower supply voltages reduce switching energy quadratically but compress the noise margin that distinguishes on from off; higher doping improves gate control but raises junction capacitance and amplifies random dopant fluctuation. Every process node is a negotiated settlement between these constraints, encoded in the fab’s process design kit. The negotiation continues below 2 nm with channel candidates such as carbon nanotubes and transition metal dichalcogenides.

What will not change is the underlying principle: a gate voltage induces an inversion layer, the inversion layer conducts, and a switch exists. That conclusion, derived from Shockley’s 1945 field-effect notebook, governs every transistor on every die, from a 7-transistor SRAM cell in L1 cache to the largest monolithic logic die yet produced.

Sources

S. M. Sze and M. K. Lee, Semiconductor Devices: Physics and Technology, 3rd ed. (Wiley, 2012). The standard graduate-level reference for device physics.
Mark Lundstrom and Jing Guo, Nanoscale Transistors: Device Physics, Modeling and Simulation (Springer, 2006). Covers short-channel effects and quantum transport.
Intel, “22nm Technology,” Intel Technology Journal, 2012. Documents the first commercial FinFET process.
Tahir Ghani et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” IEDM 2003. Covers strained-silicon channel mobility enhancement.
Samsung Foundry, “Samsung 3nm GAA Technology,” 2022 Samsung Foundry Forum white paper.
TSMC, “TSMC 2nm Technology,” 2023 Technology Symposium. Details GAAFET nanosheet architecture.
John Bardeen and Walter Brattain, “The Transistor, A Semi-Conductor Triode,” Physical Review 74, 230 (1948). The original point-contact transistor paper.
William Shockley, “A Unipolar Field-Effect Transistor,” Proceedings of the IRE 40, 1365 (1952). The theoretical foundation for the MOSFET, twelve years before it was built.
Dawon Kahng and Martin Atalla, “Silicon-Silicon Dioxide Field Induced Surface Devices,” IRE-AIEE Solid-State Device Research Conference, 1960. The first working MOSFET, built at Bell Labs.