How Chips Are Actually Fabbed: From Ingot to Package

June 10, 2026 23 min read Chemistry & Materials

semiconductorshardwaremanufacturinglithographyvlsi

Contents

Every transistor you have ever used began as a lump of ordinary sand. The path from that sand — silicon dioxide, SiO2, the mineral quartz — to a finished chip running at five gigahertz involves crystal growth at 1,420 degrees Celsius, plasma torches bombarding wafers with ions at tens of thousands of electron-volts, mirrors polished to angstrom-level smoothness to focus light generated by exploding droplets of liquid tin, and roughly five hundred individual process steps executed in sequence without a single irrecoverable error. A modern logic fab is operating simultaneously at the scale of a beachball (the 300 mm wafer) and the scale of a water molecule (a 2 nm gate dielectric). That span of twelve orders of magnitude is the central engineering challenge, and it is why a leading-edge fabrication plant costs north of $20 billion to build before a single wafer has been processed.

The transistor’s physics are covered in how a transistor actually works and the Bell Labs history behind its invention is in the Bell Labs story. This post is about manufacturing: how you go from knowing what a transistor is to making three trillion of them a year, and what it costs when you try.

Growing the crystal: the Czochralski process

Silicon is the second most abundant element in Earth’s crust, but elemental silicon — purified silicon metal — does not occur naturally; it must be smelted from quartz in arc furnaces. That yields metallurgical-grade silicon, which is roughly 98–99% pure. For electronics you need eleven nines: 99.999999999% purity, less than one foreign atom per ten billion silicon atoms. Achieving that requires the Siemens process (chemical vapor deposition of trichlorosilane, reduced by hydrogen) to produce polycrystalline electronic-grade silicon, and then the Czochralski process to grow a single crystal from the melt.

The Czochralski process works as follows: a crucible of fused quartz is loaded with electronic-grade polysilicon and melted at about 1,420 °C, just above silicon’s melting point. A seed crystal — a small single-crystal silicon rod cut along a precise crystallographic axis, usually ⟨100⟩ or ⟨111⟩ — is lowered until it barely contacts the melt. The seed is then slowly rotated and withdrawn at a controlled rate, typically a few millimeters per minute. Molten silicon atoms preferentially attach to the seed’s crystal lattice structure rather than nucleating new grains, because the ordered surface is energetically favorable. The result is a single-crystal boule: a cylindrical ingot of pure silicon with one continuous crystal lattice running from one end to the other, typically 300 mm in diameter and 1–2 meters long, weighing roughly 100 kg.

A small, precisely measured dose of dopant — phosphorus for n-type silicon, boron for p-type — is added to the melt to establish the background carrier concentration of the substrate. The crystal puller maintains a narrow thermal profile; the interface between solid and liquid is a zone only a few centimeters tall, and maintaining it requires real-time control of heater power, pull rate, and rotation speed to compensate for thermal drift.

The boule is then ground to a precise diameter, marked with a flat or notch along a crystallographic axis (so equipment can align masks correctly), and sliced by a wire saw — a web of fine diamond-coated wire moving at high speed — into wafers about 775 micrometers thick. Each slice loses roughly 300 micrometers to the kerf, which is pure waste on a material worth thousands of dollars per kilogram. The cut wafers are then lapped (abraded flat), etched to remove saw damage, and polished with progressively finer slurries in a process called chemical-mechanical planarization (CMP). The final surface is polished to a roughness below 0.1 nanometers RMS — smoother, by orders of magnitude, than anything achievable by mechanical means alone — using a slurry of colloidal silica in an alkaline solution that removes material simultaneously by chemistry and abrasion. A finished prime wafer is inspected for crystal defects by laser scanning; a single unwanted crystal grain dislocating through the wafer can ruin every device built over that region.

Photolithography: writing with light

The defining step in chip manufacturing is photolithography, the process by which circuit patterns are transferred from a mask onto the wafer surface. The core idea is borrowed from photography: coat the wafer with a light-sensitive polymer called a photoresist, expose selected areas to light through a patterned mask, develop the resist (removing either the exposed or unexposed regions, depending on whether it is positive or negative tone), and use the resist as a stencil for subsequent deposition or etching.

A simplified view of a single lithography step looks like this:

  LIGHT SOURCE
       |
       |  (monochromatic, collimated)
       v
  [  MASK / RETICLE  ]   <- chrome patterns on quartz
       |
       |  4× or 5× reduction lens
       v
  [photoresist layer ]   <- light changes polymer solubility
  [  dielectric SiO2 ]
  [    silicon wafer  ]

The critical constraint is the Rayleigh diffraction limit: the minimum printable feature size scales as k₁ × λ / NA, where λ is the wavelength of the exposing light, NA is the numerical aperture of the lens, and k₁ is a process factor that captures the sophistication of the optical tricks being deployed. You cannot print features much smaller than the wavelength you are using without heroic engineering. This single equation has driven the entire history of lithography wavelength reduction:

1980s: mercury arc lamp g-line, 436 nm
1990s: mercury i-line, 365 nm
Early 2000s: KrF excimer laser, 248 nm
Mid-2000s through ~2018: ArF excimer laser, 193 nm (with immersion: 193i)
2018 onward: EUV, 13.5 nm

The transition from 248 nm to 193 nm was straightforward. The transition from 193 nm to EUV took three decades of development, cost billions of dollars in R&D, and produced one of the most remarkable machines ever engineered — one that only one company in the world knows how to build.

It is worth noting that 193 nm immersion lithography (193i), where the gap between lens and wafer is filled with deionized water (refractive index ~1.44), can achieve effective wavelengths of 193/1.44 ≈ 134 nm, dramatically extending its useful life. Combined with multiple patterning — exposing the same layer two, three, or four times with offset masks to interleave features — 193i can print structures well below 20 nm at the cost of process complexity, cycle time, and overlay accuracy. TSMC used quadruple patterning at 7 nm before EUV was production-ready, and the mask count for a single metal layer could reach six or more. The process worked; it also added weeks to cycle time and cost structures no one enjoyed.

EUV lithography: the absurd machine

Extreme ultraviolet lithography uses 13.5 nm wavelength light — in the soft X-ray range, far shorter than visible light, short enough that ordinary air absorbs it completely and ordinary glass is opaque to it. Building a machine around this wavelength requires solving approximately a dozen independently impossible engineering problems simultaneously.

The light source works as follows. Liquid tin is released as droplets roughly 30 micrometers in diameter at a rate of 50,000 droplets per second. Each droplet is hit by a low-power pre-pulse laser that flattens it into a disk; then a second, high-power CO2 laser pulse (about 20–30 kilowatts peak) vaporizes and ionizes the tin disk. The resulting plasma, briefly at temperatures exceeding 400,000 degrees Celsius, radiates strongly at 13.5 nm as electrons cascade through the energy levels of multiply-ionized tin ions (specifically Sn IX through Sn XIV). The light is emitted in all directions; an elliptical collector mirror captures roughly 2% of the total emission and directs it into the illumination optics.

The conversion efficiency from laser light to usable 13.5 nm in-band EUV light is around 5–6% (with optimized pre-pulse shaping). When you account for the rest of the optical train — collector reflectivity, condenser, and projection optics — the overall wall-plug efficiency from electrical power to photons arriving at the wafer is roughly 0.02%. The machine consumes roughly a megawatt; it delivers a few watts of EUV at the wafer plane. This is not an engineering failure; it is the best possible result given the physics of the wavelength.

Because 13.5 nm light is absorbed by everything — air, glass, most metals — the entire optical path operates in near-total vacuum, and all optical elements must be reflective rather than refractive. A set of six aspherical mirrors, each figured to better than 0.1 nm surface roughness and coated with 40–50 alternating bilayers of molybdenum and silicon (Mo/Si multilayer), redirect and focus the beam with a combined reflectivity of roughly 35%. The masks are also reflective: EUV reticles are quartz substrates with Mo/Si multilayer coatings, with patterned absorber layers on top. Any particulate contamination on any mirror degrades the entire system; each mirror must be kept cleaner than an operating room.

The result is a machine weighing roughly 160 tonnes, occupying two floors of a fab building, assembled from tens of thousands of custom parts, and requiring a dedicated supply chain of hundreds of specialized suppliers across Europe, Japan, and the United States. ASML in Eindhoven is the only company that has managed to integrate all of this into a production tool. In 2025 they sold 48 EUV systems, generating approximately 11.6 billion euros in EUV-related revenue. Each tool is priced at approximately $200 million; the newer High-NA EUV (Twinscan EXE:5200 series, NA 0.55 versus 0.33 for standard EUV) costs approximately $380 million per unit. There is no second source. ASML does not have a competitor in EUV; it has customers.

Parameter	DUV (ArF immersion)	EUV (0.33 NA)	High-NA EUV (0.55 NA)
Wavelength	193 nm	13.5 nm	13.5 nm
Numerical aperture	1.35 (immersion)	0.33	0.55
Min. half-pitch (single exposure)	~38 nm	~13 nm	~8 nm
Optics type	Refractive (glass)	Reflective (Mo/Si mirrors)	Reflective (anamorphic mirrors)
Typical throughput	~250 wafers/hr	~170 wafers/hr	~90–120 wafers/hr
Approximate tool cost	$50–80M	~$200M	~$380M
Production-ready at	90 nm (2003)	7 nm (2018)	2 nm / 14A (~2027–28)

Intel received its first production High-NA EUV tool in July 2025, the first chipmaker to do so. TSMC plans to deploy High-NA EUV at its 1.4 nm (A14) node around 2028; Samsung is reportedly acquiring High-NA EUV tools for 2 nm foundry production.

Deposition and etching: building the stack

A finished chip is not a flat surface — it is a three-dimensional structure, built up from dozens of stacked layers of different materials. Between lithography exposures, the fab alternates between adding material (deposition) and removing it (etching). Understanding the sequence is essential to understanding why fabrication requires so many steps.

Physical vapor deposition (PVD) is conceptually the simplest: a target of the desired material (aluminum, titanium, copper) is bombarded by ions in a vacuum, sputtering atoms off the target and onto the wafer. PVD is fast and controllable but has poor conformality — it struggles to coat the walls of narrow trenches and holes uniformly.

Chemical vapor deposition (CVD) uses gas-phase chemistry: precursor gases are introduced into a heated chamber and react at the wafer surface to deposit a solid film. Plasma-enhanced CVD (PECVD) runs at lower temperatures by using plasma to activate the reaction. CVD is far more conformal than PVD and can deposit silicon dioxide, silicon nitride, tungsten, and many other materials with good uniformity. Subatmospheric CVD and high-density plasma CVD are used for gap-fill: depositing material into narrow spaces between metal lines without voids.

Atomic layer deposition (ALD) takes conformality to its logical extreme. Rather than a continuous gas flow, ALD exposes the wafer to precursor A (which chemisorbs, self-limiting, to a single monolayer), purges the chamber, exposes it to precursor B (which reacts with the adsorbed layer to form the desired film and releases byproducts), and purges again. Each complete cycle deposits typically 0.1–0.2 nm — roughly one atomic layer. The self-limiting nature of the surface reactions means that ALD is perfectly conformal regardless of geometry: every surface, including deep trench walls and the undersides of overhangs, receives exactly the same thickness. This is the only deposition technique capable of reliably depositing the high-k dielectrics (hafnium oxide, HfO2) used as gate dielectrics in modern FinFETs and GAAFETs, which must be 1–2 nm thick with zero pinholes.

Wet etching uses liquid chemical solutions — hydrofluoric acid for oxide, phosphoric acid for nitride, potassium hydroxide for silicon. It is isotropic (etches equally in all directions) and selective (chooses the target material over adjacent materials), but the isotropic nature means it undercuts features laterally, limiting its use in high-resolution patterning. Wet etching is used for cleans, blanket film removal, and processes where isotropy is acceptable.

Dry etching (plasma etching / RIE) uses a low-pressure plasma to generate reactive radical species and ion bombardment. Reactive ion etching (RIE) is directional: ions are accelerated toward the wafer perpendicular to its surface, so etching proceeds preferentially downward with vertical sidewalls. Inductively coupled plasma RIE (ICP-RIE) and deep reactive ion etching (DRIE) can achieve aspect ratios of 50:1 or more, essential for contact holes and vias. The chemistry is tunable: fluorine-based plasmas (SF6, CF4) etch silicon and oxide; chlorine-based plasmas (Cl2, BCl3) etch aluminum and many metals; bromine-based chemistries etch polysilicon with high selectivity.

A cross-sectional view through a partially fabricated wafer at a gate region looks roughly like this:

         GATE STACK (simplified)
  ┌─────────────────────────────────┐
  │   metal gate (W or TiN)         │   <- deposited by CVD/ALD
  │   high-k dielectric (HfO2)      │   <- 1-2 nm, ALD
  ├───────┬─────────────┬───────────┤
  │ SiO2  │ FinFET body │  SiO2     │   <- isolation
  │ (STI) │ (Si or SiGe)│  (STI)    │
  ├───────┴─────────────┴───────────┤
  │     p-type silicon substrate    │
  └─────────────────────────────────┘

The complete layer stack for a modern logic chip — gate oxide, multiple metal interconnect layers (M0 through M10 or higher), vias, barrier layers, capping layers — requires alternating deposition and etching sequences dozens of times. Intel’s 20A process and TSMC’s N2 both use “backside power delivery,” routing the power rails on the reverse of the wafer to free up routing resources on the front, which adds another complete set of process steps on the wafer’s back surface.

Doping by ion implantation

Doping — introducing controlled concentrations of donor (phosphorus, arsenic) or acceptor (boron, indium) impurities — is what makes transistors work. In early semiconductor manufacturing this was done by diffusion: expose the silicon to a dopant-containing gas at high temperature and let atoms drift in. Diffusion is uncontrollable at the scales of modern devices: the thermal budget required to drive atoms to sufficient depth also causes previously implanted regions to spread and contaminate neighboring structures.

Ion implantation replaced diffusion as the primary doping technique in the 1970s and is now universal. A dopant element (boron, phosphorus, arsenic, etc.) is ionized, accelerated through a precisely tuned electric field to a kinetic energy between a few keV and a few MeV, and fired at the wafer as a beam. The ions penetrate the silicon to a depth determined by their energy and mass — this is adjustable and reproducible to better than 1% — and come to rest in a roughly Gaussian distribution. The dose (atoms per square centimeter) is controlled by measuring the beam current and integrating over time.

After implantation, the crystal lattice is damaged — the incoming ions collide with and displace silicon atoms. A rapid thermal anneal (RTA) at 900–1100 °C for a few seconds, or a flash anneal (millisecond time scales), heats the silicon long enough to allow displaced atoms to return to lattice sites (recrystallize) and activate the dopant electrically (incorporate it into substitutional lattice positions where it donates or accepts carriers), without giving the dopant atoms time to diffuse significantly. Flash anneals using laser pulses can heat the surface to near-melting for microseconds while the bulk wafer stays cool, achieving abrupt dopant profiles that are physically impossible with conventional furnace anneals.

At sub-5 nm gate lengths, even implantation-and-anneal is being supplemented or replaced: the channel regions of GAAFETs may be doped by in-situ doping during epitaxial silicon growth, where dopant gases are mixed into the silicon precursor during the CVD process to produce doped layers with atomic-layer precision. The physics of the transistor is the same; the methods of achieving it continue to evolve.

The 500-step reality

A simple textbook description of chip manufacturing gives you five steps: deposit, pattern, etch, dope, metallize. A real process flow for a leading-edge logic chip runs to approximately 500 or more discrete processing steps, each of which must be executed within tight specification windows, often on equipment worth $50–200 million per tool, in a cleanroom that must maintain particulate counts below ISO Class 1 levels (fewer than 10 particles per cubic meter larger than 0.1 micrometers). Any particle that lands on a wafer surface in the wrong place at the wrong time can kill the die underneath it.

The full flow for a single-patterned metal layer, to take one example, involves: chemical-mechanical polishing of the previous layer, surface clean, ALD barrier layer deposition, photoresist coat and bake, EUV exposure, post-exposure bake, develop, resist inspection, plasma etch of the metal layer or dielectric trench, resist strip and ash, another clean, gap-fill deposition, CMP to planarize, endpoint detection, and post-CMP clean. That is roughly 15–20 steps for one layer, and a chip might have 15 metal layers plus the complete transistor front-end flow. The transistor front end alone — shallow trench isolation, gate stack deposition, gate patterning (potentially requiring multiple patterning), source/drain epitaxy, spacer formation, contact silicidation — accounts for 150 or more steps before the first metal line is ever drawn.

The time from bare silicon wafer to finished die is typically 10–14 weeks at a leading-edge fab, even running 24/7 with wafers moving continuously between tools. This cycle time is itself a competitive variable: a fab that can turn wafers in 9 weeks instead of 12 gets design feedback to customers faster and makes more money on each tool installation.

Defects and yield

Yield is the fraction of die on a wafer that pass all electrical tests and are suitable for sale. It is the financial heartbeat of a semiconductor company. A fab that achieves 90% yield on a process prints money; a fab at 50% yield on the same process may not cover its costs. The relationship between yield and profitability is highly nonlinear, because the fixed cost of running a fab is enormous regardless of how many good chips come out.

The dominant model for yield estimation is the Poisson model or the Murphy model, both of which relate yield to defect density and die area: Y ≈ e^(−D₀ × A), where D₀ is defects per unit area and A is die area. The implication is brutal: large die lose yield exponentially. A die that is twice as large has roughly squared probability of catching a killer defect. This is why, historically, the first generation of chips at a new node tends to be small: graphics shaders, baseband processors, microcontrollers — things where die size stays under 50 mm². The big-die, high-margin parts (CPUs, GPUs, AI accelerators) wait for the process to mature and defect density to fall.

Year	Node	Transistors per die (example)	Key chip
1971	10 µm	2,300	Intel 4004
1978	3 µm	29,000	Intel 8086
1989	1 µm	1,200,000	Intel 486
2000	180 nm	42,000,000	AMD Athlon
2006	65 nm	291,000,000	Intel Core 2 Duo
2012	22 nm	1,400,000,000	Intel Ivy Bridge
2017	10 nm	3,000,000,000	Apple A11
2020	5 nm	11,800,000,000	Apple A14
2022	3 nm	16,000,000,000	Apple A16
2025	2 nm	~20,000,000,000	Apple A19 (projected)

The chiplet strategy is, at its core, a yield engineering decision. A 800 mm² monolithic GPU die at 2 nm would have catastrophically low yield — perhaps single-digit percentages. Break that into four 200 mm² chiplets, and each one yields independently at a much higher rate; the overall multi-chip module yield is the product of the individual die yields (corrected for known-good-die testing), but because the yield curves are shallow at smaller die sizes, the math comes out ahead. AMD’s EPYC and Ryzen processors moved to chiplets for exactly this reason: the 5 nm compute chiplets (CCDs) are small enough to yield well, while the I/O die remains on the older, cheaper 12 nm node where it yields at near-100%. NVIDIA’s Blackwell uses CoWoS (chip-on-wafer-on-substrate) to stitch two reticle-limited GPC dies together with HBM memory stacks; the architecture is driven partly by the physics of compute and partly by the hard ceiling on what a single reticle can expose in one shot (~858 mm² on TSMC EUV tools).

Packaging: from die to device

A finished wafer comes out of the fab as a grid of tested die, each one electrically functional (or flagged as dead) but mechanically fragile and entirely useless without connections to the outside world. Packaging converts a bare die into something that can be soldered to a circuit board, cooled, and powered.

Wire bonding is the oldest and still most common technique at volume. The die is attached face-up to a lead frame or substrate, and fine wires (gold, copper, or silver, 15–50 micrometers in diameter) are thermosonically bonded from pads on the die edge to the package leads. Wire bonding is cheap and flexible but slow (bonds are made one at a time), limited in density (pad pitch below ~50 µm is challenging), and adds resistance and inductance in the bond wire itself.

Flip chip inverts the die face-down onto the substrate, with solder bumps (originally SnPb solder balls, now lead-free SnAgCu alloys) connecting die pads directly to substrate pads underneath. Bumps can be arrayed across the entire die area, not just the edge, enabling far higher I/O density. The short, fat bump connections have lower inductance and better thermal characteristics than wire bonds. Virtually all high-performance processors (CPUs, GPUs, AI accelerators) use flip chip; the underfill epoxy injected beneath the die after bumping provides mechanical reliability against thermal cycling. The solder metallurgy involved — eutectic points, intermetallic compound growth, thermal fatigue — is a deep field in its own right.

Advanced packaging goes further, integrating multiple die and memory in the same package at interconnect densities that would have been considered on-chip density a decade ago.

CoWoS (Chip on Wafer on Substrate), TSMC’s primary advanced packaging platform, places die face-down on a silicon or glass interposer — an intermediate substrate with fine copper redistribution layers that creates short, low-loss connections between chiplets. The interposer is fabricated on a standard wafer flow, diced, and mounted on an organic substrate. CoWoS-L (Local Silicon Interconnect) uses embedded silicon bridges for the densest chiplet-to-chiplet connections, while CoWoS-R uses a smaller RDL (redistribution layer) interposer. NVIDIA secured over 70% of TSMC’s CoWoS-L capacity in 2025 to support Blackwell production.

HBM (High Bandwidth Memory) stacks DRAM dies vertically using through-silicon vias (TSVs): vertical conductors etched through the full thickness of the silicon and filled with copper, connecting the I/O of each stacked die. An HBM4 stack might include 16 DRAM dies bonded on top of each other plus a base logic die, with thousands of TSVs providing a 1,024-bit-wide memory interface that achieves memory bandwidth exceeding 1.5 TB/s — impossible with conventional DDR DRAM regardless of clock speed.

Why fabs cost $20 billion

The capital intensity of a leading-edge fab is extraordinary even by heavy industrial standards. A steel mill, a petrochemical plant, an automobile factory — all are expensive. None approaches $20 billion for a single facility. Several factors drive this:

Equipment cost. A complete set of lithography, etch, deposition, CMP, implant, metrology, and inspection tools to equip a 300 mm wafer fab costs $10–15 billion in equipment alone. A single EUV scanner is $200 million; a leading fab needs 15 or more of them for a 50,000 wafer-per-month capacity. High-NA EUV tools cost approximately $380 million each. Metrology and inspection tools — scanning electron microscopes, overlay metrology tools, defect review stations — run $5–15 million per unit and are needed in multiples.

Cleanroom construction. The fab building itself must maintain ISO Class 1 to Class 3 cleanliness throughout the tool bay. This requires HEPA and ULPA filtration systems, positive pressure differentials, vibration isolation (epitaxy and lithography tools require vibration levels below nanometers), and chemical delivery infrastructure. The building structure is typically cast concrete on massive isolation pads; the HVAC systems are often larger than the process equipment.

Yield learning. A new fab does not immediately produce chips at mature yield. The process engineers spend 12–24 months after first tool-in learning the specific tool interactions, contamination sources, and process drifts of that facility. During ramp, yield may be 30–50%; every wafer run at low yield is a wafer-cost loss that must be amortized against future production.

Ongoing capital. Leading-edge process nodes advance on roughly 2–3 year cycles, and each node transition requires substantial requalification and partial tool replacement. TSMC announced capital expenditure of $38–42 billion for 2025 alone — not to build one fab, but to expand nine production facilities simultaneously and fund High-NA EUV tool purchases in anticipation of the 1.4 nm node.

TSMC’s Arizona investment has grown from $12 billion (announced 2020) to a projected $165 billion through the end of the decade, making it the largest private manufacturing investment in American history. Intel’s Ohio fab complex, if completed, is projected to exceed $100 billion. These numbers reflect a geopolitical calculation as much as an economic one: semiconductor supply chain concentration in Taiwan is considered a systemic risk by governments on both sides of the Pacific, and $20 billion fabs are, apparently, what national industrial policy costs.

Verdict

Semiconductor fabrication is the most precise large-scale manufacturing process humans have ever developed. Its dominant physical constraint — the Rayleigh diffraction limit — forced the industry to develop a light source that did not exist in any catalog (EUV), a mirror-polishing technology beyond anything in astronomy, and a supply chain so specialized that a single Dutch company controls whether the world’s advanced chips ship. The economics of yield drive architectures: chiplets are not a product of elegant engineering preference but of the brute mathematics of large die on a process that kills die exponentially with area. The $20 billion fab is not a monument to ambition; it is the minimum viable investment to do the physics at all.

What comes next is not reassuring in its simplicity. Gate-all-around FETs (already in production at Samsung’s 3 nm and TSMC’s N2) make the transistor three-dimensional in a second dimension. Backside power delivery routes power below the transistor plane. 2D materials (MoS2, WSe2) with single-atom-thick channels are in research. High-NA EUV will push half-pitch below 8 nm. And at some point in the 2030s, gate lengths will approach dimensions where quantum tunneling becomes the primary current mechanism and the classical transistor model breaks down entirely. When that happens, the industry will face either a new device physics or the first genuine end to geometric scaling in seventy years. Given the track record, it would be unwise to bet against the engineers.