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3D NAND Architecture: Building Memory Sideways, Then Up

10 min read The Physics of Computing
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Contents

For forty years, making memory denser meant making it smaller. Planar NAND rode lithography from micron-scale cells down to 15 nanometers, and then — almost uniquely in semiconductors — the industry stopped shrinking, turned the structure on its side, and started building up instead. Modern 3D NAND is not planar NAND with more layers; it is a different device (charge-trap instead of floating-gate, in most cases), a different transistor geometry (gate-all-around cylinders), a different manufacturing economics (etch- and deposition-bound instead of litho-bound), and a different scaling law (add layers, not shrink features). It is also, quietly, the most aggressive vertical manufacturing humanity does: a current-generation die etches trillions of holes with aspect ratios that would embarrass an oil-drilling operation, through more than 300 alternating films, and lands every one of them within nanometers. This post explains how the structure works, why each architectural choice was forced, and what the choices cost — from first principles to the level where vendor roadmap slides start making sense.

Why Planar Died

A planar NAND cell stores charge on a floating gate patterned lithographically on the silicon surface (the transistor explainer covers the underlying MOSFET; the flash-storage primer the storage physics). Shrinking it ran into three compounding walls in the mid-2010s, around the 15–16nm node:

Counting electrons. Cell capacitance scales with area. At 15nm, the charge separating adjacent Vt states was down to a few tens of electrons — single-digit electrons per state boundary in the worst corners. Lose three electrons to leakage and you’ve moved a measurable fraction of a state. The statistics of small numbers were eating the read window faster than ECC could buy it back (the budget framing is in the read-window-budget analysis).

Talking neighbors. Floating gates are conductors sitting next to each other; at small pitch, the capacitive coupling between adjacent cells meant programming one cell visibly shifted its neighbor’s apparent Vt. Mitigation (program-order choreography, coupling compensation) consumed design complexity and margin and got worse every shrink.

Paying for lithography. Below ~20nm, NAND needed multi-patterning on every critical layer. Each shrink bought less density per dollar than the one before. The economic engine — cost per bit falling every node — was sputtering precisely when the physics was worst.

The escape was articulated by Toshiba’s BiCS (Bit-Cost Scalable) research in 2007 and shipped at scale by Samsung in 2013 as V-NAND: stop patterning cells laterally, and instead deposit many cheap, unpatterned film layers and form cells along a vertical channel punched through all of them at once. Density now scales with layer count, which depends on deposition and etch — not on lithography at all. The critical dimensions of a 3D NAND cell are tens of nanometers and have barely changed in a decade; the layer count went from 24 to past 300.

The Vertical String

The unit structure of 3D NAND is a vertical NAND string: dozens to hundreds of cells in series along a cylindrical channel, with horizontal word-line plates wrapping each cell.

            bit line (top, metal)
                 |
            [SGD select transistor]
                 |
   WL_n   =====(cell)=====   <- word line plate wraps the
   WL_n-1 =====(cell)=====      channel as a full cylinder:
   ...    =====(cell)=====      gate-all-around
   (dummy WLs)
   ...    =====(cell)=====
   WL_1   =====(cell)=====
   WL_0   =====(cell)=====
                 |
            [SGS select transistor]
                 |
            source line (bottom)

   Channel hole cross-section (one cell):

        +---------------------------+
        |   word line (gate metal)  |
        |  +---------------------+  |
        |  |  blocking oxide     |  |
        |  |  +---------------+  |  |
        |  |  | nitride trap  |  |  |   <- charge stored HERE,
        |  |  |  +---------+  |  |  |      in an insulator
        |  |  |  | tunnel  |  |  |  |
        |  |  |  |  oxide  |  |  |  |
        |  |  |  | +-----+ |  |  |  |
        |  |  |  | |poly | |  |  |  |   <- thin polysilicon
        |  |  |  | |chan.| |  |  |  |      channel (macaroni)
        +--+--+--+-+-----+-+--+--+--+

The manufacturing sequence that produces this is called punch-and-plug. Deposit an alternating stack of films (oxide/nitride pairs in the dominant replacement-gate flow). Etch the channel holes — billions of them per die, through the entire stack in one step. Line each hole’s wall with the blocking oxide, the charge-trap nitride, and the tunnel oxide; fill the core with a thin polysilicon channel. Then etch slits, dissolve the sacrificial nitride layers, and backfill the voids with tungsten word lines. Every cell on a word line shares one physical plate; every cell in a string shares one physical channel.

The channel-hole etch is the gating step of the entire technology. The holes are ~100nm wide and several microns deep — aspect ratios beyond 60:1 — and the etch must keep billions of them per die straight, round, and uniform. It cannot, entirely: holes taper, narrower at the bottom than the top, so cells at different heights in the stack have measurably different geometry, coupling, and program behavior. That taper is why per-word-line-group trim offsets exist (set by factory trim calibration), why characterization is always cut by layer, and why “which word line?” is the first question in any 3D NAND failure analysis.

Charge trap vs floating gate

Most 3D NAND abandoned the floating gate for a charge trap: electrons are stored in a silicon-nitride insulator rather than on a conductive gate. Trapped charge in an insulator doesn’t redistribute, which kills the neighbor-coupling problem and tolerates point defects in the tunnel oxide (a single leak path drains a floating gate completely; it drains a charge trap only locally). The costs are honest: trapped charge migrates slowly within the nitride over long retention periods, and erase requires different mechanics. Micron notably carried floating-gate into its first 3D generations (with CMOS under the array as compensation) before converging on charge-trap replacement-gate at its 176-layer generation — a useful reminder that these architecture choices are portfolios of trade-offs, not settled science.

Scaling Up: Stacking, Decks, and the Peripheral Problem

String stacking. A single etch can only punch so deep before taper and twist destroy uniformity. Past roughly 100 layers, vendors build the stack in two or more decks: etch and fill the first deck, deposit the second stack on top, etch again, and join the channels. The deck joint is a real electrical feature — alignment between deck holes is imperfect, and the cells adjacent to the joint behave differently enough to get dummy word lines and their own trim treatment. Layer-count headlines are deck sums: a “321-layer” device is not one miraculous etch.

Where the logic goes. A NAND die also needs CMOS periphery — sense amplifiers, charge pumps, decoders, the interface. Three placements define the generations:

Approach Idea Trade-off
Periphery beside array Classic planar floorplan carried into early 3D Burns die area; array efficiency ~70%
CMOS under Array (CuA/PUA) Build logic first, array on top of it Recovers area (85%+ array efficiency); logic endures array thermal processing, limiting transistor quality
Bonded (Xtacking / CBA) Build array and CMOS on separate wafers, bond face-to-face Best of both: optimal logic process AND full-area array; costs a second wafer and a bonding step

YMTC’s Xtacking shipped wafer bonding first; Kioxia/Western Digital’s BiCS8 (“CBA” — CMOS directly Bonded to Array) and Samsung’s roadmap followed the same direction. Bonding matters beyond density: interface logic built on an unconstrained CMOS process is how NAND I/O reached 3,600 MT/s, and it foreshadows the architectural future — memory as stacked, heterogeneous, bonded silicon rather than monolithic die (what comes after NAND picks up that thread).

The current state of the race. As of this writing, the 300-layer class is in production across the majors — Samsung’s V9, SK hynix at 321 layers, Micron’s G9 generation, Kioxia/WD BiCS8 in the 200+ class with bonding — with 400+ layer generations announced on every roadmap. Layer growth has slowed from its early doubling cadence: each added layer increases etch depth, stress (a thick tungsten-laced stack literally bows the wafer), and cycle time, so the per-generation gain is now also harvested from logical scaling — more bits per cell (the QLC/PLC density endgame), tighter hole pitch, and bonding-recovered area — rather than layers alone.

What the Architecture Costs You

Every structural choice above surfaces as a behavior that product and systems engineers live with:

Giant blocks. The erase unit in 3D NAND is a block spanning the full stack height, and layer growth inflated it: blocks are now tens of megabytes against the single-digit megabytes of late planar. Bigger blocks mean coarser garbage-collection granularity, more data movement per reclaim, and worse write amplification for small random writes — an architectural decision made in the etch bay that an FTL engineer pays for years later.

Series-string electrical reality. Reading one cell requires every other cell in its string — potentially 300+ of them — to conduct, which means driving every unselected word line to a pass voltage. More layers per string lowers read current, slows sensing, and multiplies read-disturb exposure (each read of any page weakly stresses the whole string). Dummy word lines at string ends, deck joints, and layer boundaries absorb the worst edge effects and quietly subtract from advertised density.

Layer as a first-class variable. Taper makes the stack a gradient of slightly different devices. Vendors bin word lines into groups with separate trims, separate program staging, sometimes separate ECC provisioning. The practical consequence: distributions, error rates, and failure statistics in 3D NAND are always per-layer-group data, and any analysis that averages across the stack is hiding the tail that will actually fail.

Thermal and stress engineering. Hundreds of alternating films plus tungsten fill create enormous mechanical stress; wafer bow and layer-to-layer alignment consume real process margin. The array’s thermal budget constrains everything built under it — one of the quiet arguments for bonding.

None of these are flaws; they’re the purchase price of the only scaling path that worked. The honest comparison is against the counterfactual: planar NAND at 15nm was a worse device by every one of these measures and couldn’t get cheaper.

Verdict

3D NAND is what an industry does when its scaling law dies and the demand curve doesn’t care: it found a dimension nobody was using and industrialized it. The conceptual core is small — cells along a vertical channel, word lines as wrapped plates, charge stored in an insulator, density bought with deposition and etch instead of lithography — and everything else is consequence management: taper becomes per-layer trims, depth limits become deck joints, periphery area becomes CuA and then wafer bonding, string length becomes read-disturb policy and giant blocks become FTL pain. For a newcomer, the load-bearing insight is that “more layers” is not “the same chip, taller” — each layer-count generation renegotiates etch physics, stress, block geometry, and per-layer variation. For practitioners, the architecture explains the daily texture of the work: why characterization is cut by word-line group, why block sizes keep growing, why I/O speed jumped when bonding arrived, and why the roadmap now leans on bits-per-cell and bonding as much as layer count. The vertical turn bought the industry a decade and a half of scaling. The next trick — covered in the density-endgame and post-NAND posts — is figuring out what happens when this dimension gets expensive too.

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