How Semiconductors Are Tested

June 12, 2026 20 min read The Physics of Computing

semiconductorstestatewafer-sortmanufacturingreliability

Contents

Every die that ships has been individually interrogated by a machine that costs more than a house, and the result of that interrogation — pass, bin 3, fail, retest — is the single fact that turns a slab of patterned silicon into a product you can buy. A fab produces candidates. Test produces parts. The gap between those two words is where billions of dollars and the entire credibility of a datasheet live. Test is not a quality-assurance afterthought bolted onto manufacturing; it is a co-equal manufacturing step whose cost, throughput, and statistical philosophy shape the chip’s price, its reliability, and what the vendor is legally and contractually promising you. A modern part can spend a meaningful fraction of its total cost being measured, and the engineers who own that measurement spend their careers fighting two enemies that pull in opposite directions: the seconds of tester time that bleed margin on every unit, and the escaped defects that bleed reputation one field return at a time.

This post walks the flow a die actually travels — probe at the wafer, assembly, final test, optional burn-in, and the adaptive screens layered on top — then digs into the economics and statistics a test or product engineer lives inside. If you want the upstream story of where the defects come from, that is yield engineering; this is the story of how we find them.

The Flow: Sort, Assemble, Final Test, Burn-In

Silicon is tested at least twice, and increasingly more than that. The reason is economic, not technical: you want to throw away bad material at the cheapest possible point, before you spend money packaging it. A bare die is cheap to discard. A die that has been singulated, attached to a substrate, wire-bonded or bumped, encapsulated, and marked has absorbed real assembly cost — so screening before assembly (wafer sort) and after assembly (final test) catches different failure populations at different price points.

   WAFER FAB                 SORT / PROBE              ASSEMBLY
  +-----------+   wafers    +-------------+  good     +-----------+
  | litho,    |------------>| probe card  |  die map  | singulate |
  | etch,     |   (KGD?)    | + ATE: DC,  |---------->| die-attach|
  | implant,  |             | continuity, |           | bond/bump |
  | metal ... |             | functional, |           | mold/mark |
  +-----------+             | bin & ink   |           +-----+-----+
                            +-------------+                 |
                                                            v
   SHIP <----+  FINAL TEST  <----+  BURN-IN  <----+   PACKAGED PART
             |  (FT1/FT2):       |  (optional):   |   on a loadboard
             |  full functional, |  voltage +     |   in a handler
             |  speed binning,    |  temp stress, |
             |  AC/DC params,     |  hours, then  |
             |  outlier screens   |  retest       |
             +-------------------+----------------+

At wafer sort (also called wafer probe or, on memory lines, “wafer test”), the wafer is held on a chuck and a prober steps it under a probe card whose needles or springs land on the die’s bond pads or bumps. The card is wired to automated test equipment (ATE) — the tester — which drives stimulus and measures response. Sort does the cheap, decisive screens: opens/shorts (continuity), gross DC parametrics, leakage, and enough functional pattern to separate dead die from live ones. The output is a wafer map — a per-die pass/fail (and bin) record — and historically an ink dot on rejects; modern lines skip the ink and carry the map digitally so the pick-and-place at assembly only mounts good die.

After assembly, the now-packaged part goes to final test (FT). Here the part is socketed on a loadboard in a handler (which also sets temperature), and the ATE runs the full datasheet: AC and DC parametrics, full functional and structural patterns, and — critically — speed binning, where the same physical design is sorted into SKUs by the maximum frequency it actually passes. The Core i7 and the Core i5 can be the same die; final test decided which one you got. Final test may be split into a hot insertion and a cold insertion (FT1/FT2) because timing margins and leakage move with temperature, and some defects only show up at one corner.

Burn-in sits between or after final test for parts that demand it: the packaged device is powered up at elevated voltage and temperature for hours to accelerate latent defects to failure before shipment. It is expensive and not universal — more on its economics below.

Stage	Device form	What it screens	Relative cost of a scrap
Wafer sort (probe)	Bare die on wafer	Opens/shorts, gross DC, basic functional, redundancy repair	Lowest — just the silicon area
Final test (FT)	Packaged part	Full AC/DC, functional, speed bin, outlier screens	High — silicon + assembly + package
Burn-in	Packaged part (powered)	Infant-mortality / latent reliability defects	Highest — adds hours of socket + oven time
System-level test (SLT)	Part in a board/system	Whole-chip interactions ATE can’t reach	Very high — slow, near-application

A failure caught at sort costs you a die. The same failure at final test costs a die plus a package; escaping past final test costs a customer return; escaping into a car or a data center costs a recall. Every dollar test spends is justified by the larger dollar it prevents downstream — the same logic that drives failure analysis from RMA to root cause when a part does escape.

Probe Cards: The Mechanical Interface Nobody Talks About

The glamour in test goes to the ATE, but the part that most often limits what you can do is the probe card — the precision interface that has to make hundreds or thousands of temporary electrical contacts to pads or bumps that may be smaller than 40 micrometers across, repeatedly, without damaging them, across a full wafer and across hundreds of thousands of touchdowns of card life.

There are three broad families:

Cantilever (needle) cards — angled tungsten needles, cheap and serviceable, good for low pin counts and parametric/RF work, poor for fine pitch and high parallelism.
Vertical / buckling-beam cards (e.g., Cobra-style) — spring pins in a guide plate that buckle predictably under load; high pin counts, better pitch, the workhorse for logic SoCs.
MEMS / advanced probe (e.g., FormFactor’s MEMS heads) — lithographically defined spring contacts that reach the sub-40 micrometer pitch and multi-GHz signaling that leading nodes demand.

The card is custom-engineered per die design, and for a leading-edge accelerator it can cost several hundred thousand dollars. Three constraints make it hard: planarity (every tip must land within a few micrometers of the same plane, or high tips over-drive while low tips never contact), overtravel and scrub (the card pushes past first-touch a controlled distance so tips scrub through native oxide — too little gives an open, too much craters the pad), and contact resistance stability over thousands of touchdowns as tips wear and pick up debris. A degraded card produces yield loss that looks exactly like a fab defect until someone correlates failures to a specific card or site.

Probing has also become a supply constraint in its own right. As pad pitch drops below 40 micrometers and signal frequencies climb into the multi-gigahertz range, probe-card lead times stretch, and a vendor ramping a new product can be gated by probe-card availability as surely as by wafer starts.

ATE Economics: Why Testers Cost Millions

A wafer probe station runs on the order of half a million dollars; a full ATE system commonly starts around a million and climbs from there. Why so much for a “test machine”?

Because an ATE is not one instrument — it is hundreds or thousands of synchronized instruments. Each tester channel sources and measures with picosecond timing and millivolt/microamp resolution, drives and compares digital patterns at full device speed, and does so for every pin on every one of the N devices in parallel. A high-pin-count SoC tester carries thousands of channels; a memory tester drives hundreds of devices at once at multi-Gbps I/O. You are buying precision times channel count times parallelism, plus the per-instrument calibration that keeps site 1 agreeing with site 256.

The market reflects how hard this is: Advantest and Teradyne together hold roughly 95% of the ATE market. Advantest’s V93000 dominates high-end SoC and memory (DRAM, NAND, HBM); Teradyne’s FLEX/UltraFlex and J750 lines cover advanced SoC and high-volume commodity/microcontroller test. This is a duopoly for the same reason lithography is — the engineering moat is enormous, and the install base, software, and program libraries lock customers in.

The capital number that actually matters to a test engineer is the tester time rate — the fully burdened cost of one second of that machine’s life:

tester_rate ($/sec) = (capital_recovery + maintenance + floor + labor + handler/prober)
                      / (seconds_available_per_year * utilization)

Worked example (illustrative):
  Tester + handler + prober capital     = $3,000,000
  Depreciate over 5 years               = $600,000/yr
  Maintenance + facilities + labor      = $400,000/yr
  Total annual cost                     = $1,000,000/yr
  Seconds/year (24x7)                   = 31,536,000
  Utilization (uptime * loaded)         = 0.70
  Effective seconds                     = 22,075,200
  tester_rate                           = $1,000,000 / 22,075,200
                                        = $0.0453 /second

Roughly four and a half cents per second. That number is the bridge between “how the machine works” and “what a part costs” — and it is why everything else in this post is, ultimately, about time.

Test Time Is a Unit-Cost Line Item

Here is the part newcomers underestimate: test time is not overhead, it is bill-of-materials. Every second the tester spends on a device is bought at the tester rate, divided by how many devices share that second.

test_cost_per_unit = (tester_rate * test_time_seconds) / sites_in_parallel
                     + handler_index_overhead_share

Example, two scenarios at $0.0453/sec:
  Single-site final test, 8.0 s test time:
     (0.0453 * 8.0) / 1   = $0.362 /unit
  16-site final test, same 8.0 s:
     (0.0453 * 8.0) / 16  = $0.0226 /unit

That is a 16x swing from one knob: multisite parallelism. For a commodity part selling for a few dollars, $0.36 of test cost is catastrophic and $0.023 is tolerable. For memory — high volume, low ASP — test can be a larger fraction of total IC cost than for an expensive logic chip, which is precisely why memory testers are engineered to run 128, 256, or more devices in parallel, and why memory probe cards are dense multisite arrays.

Test engineers attack the cost per unit on three fronts:

Reduce test time — drop redundant patterns, parallelize on-tester operations, replace slow functional vectors with structural test (scan/BIST) that covers the same faults faster, and cut “guardband seconds” spent settling and re-measuring.
Raise parallelism — more sites per touchdown, but this fights probe-card cost, tester channel count, and site-to-site variation (calibration differences that make site 12 read 30 mV off from site 1 and bin good parts as fails).
Raise utilization — index time (the handler/prober moving the next device into place) is dead time you still pay for; conversion kits, dual-stage handlers, and keeping the tester out of “waiting for material” states all matter.

The discipline is unforgiving: a test program that runs 9 seconds instead of 8 has just raised the unit cost by an eighth, forever, on every part that program ever touches. Multiply by hundreds of millions of units and the seconds become a budget meeting. The same time-versus-coverage tension shows up in the firmware layer too — the factory calibration of NAND trim is itself a test-time cost, because every per-die measurement that sets a trim register is a measurement the tester has to pay for.

Known-Good-Die: Test’s Hardest Problem

When chips were one die in one package, sort and final test were enough. Chiplets and stacked memory broke that. If you assemble eight HBM DRAM die plus a logic die plus a GPU into one package and one die is bad, you may have to scrap the entire multi-hundred-dollar module — including the seven good die and the expensive interposer. The yield math is merciless: if each die is independently 99% good, an eight-die stack is 0.99^8 ≈ 92.3% good; at twelve die it’s 88.6%. Multiply assembly cost by that scrap rate and the economics collapse unless you can guarantee each die is good before you stack it.

That guarantee is known-good-die (KGD): a bare, unpackaged die tested to the same confidence as a packaged part. The trouble is that the cheap-at-sort logic now works against you — the screens you wanted to defer to final test (full speed, full temperature, burn-in-class reliability) must now happen at the wafer or singulated-die level, where contacting is harder and temperature control worse. KGD pushes final-test rigor backward onto bare silicon:

KGD challenge	Why it’s hard at die level
Full at-speed functional	Probe-card parasitics limit signal integrity vs. a packaged loadboard
Temperature corners	Heating/cooling a bare die on a chuck is slower and less uniform
Reliability / burn-in screen	No package to socket; needs wafer-level or carrier-based burn-in
Handling singulated die	Tiny, fragile, no leads — special carriers, more yield-at-handling loss

For HBM specifically, vendors test each DRAM die, then test the assembled stack again, because some failures are interaction failures (TSV connections, stack-level timing) that no individual die test can see. KGD does not eliminate stack-level test; it makes stack-level test affordable by ensuring you rarely scrap good silicon. It is one of the clearest places where the broader yield engineering discipline and test engineering become the same job.

Burn-In and the Infant-Mortality Problem

Semiconductor failure rates follow the classic bathtub curve: a high but falling infant-mortality region early in life, a long flat useful-life region of random failures, and a rising wear-out region at end of life. The defects that cause infant mortality — a marginal via, a contamination particle, a weak gate oxide spot — pass final test because they are not yet failures; they are latent defects that will become failures under the first weeks of field stress. The physics of how those latent defects nucleate and grow is the same physics covered in NAND reliability physics and qual; test’s job is to find the parts carrying them before the customer does.

Burn-in drags those parts down the front wall of the bathtub before shipment by applying elevated voltage and temperature so that field-years of stress compress into test-hours. The acceleration is governed by an Arrhenius model for thermal mechanisms plus a voltage term:

Acceleration factor (thermal, Arrhenius):
  AF = exp[ (Ea / k) * (1/T_use - 1/T_stress) ]

  Ea      = activation energy of the failure mechanism (eV), e.g. ~0.7 eV
  k       = Boltzmann constant = 8.617e-5 eV/K
  T_use   = use temperature in Kelvin   (e.g. 55 C = 328 K)
  T_stress= burn-in temperature in K    (e.g. 125 C = 398 K)

  AF = exp[ (0.7 / 8.617e-5) * (1/328 - 1/398) ]
     = exp[ 8123 * (0.003049 - 0.002513) ]
     = exp[ 8123 * 0.000536 ]
     = exp[ 4.35 ] ~= 78x

So ~24 h of 125 C burn-in ~= 78 * 24 h ~= 1870 use-hours ~= 78 days of field stress.

The catch is that burn-in is expensive — it adds hours of socketed, powered oven time per part, and the test cost math above turns those hours into real money. So burn-in is a risk calculation, not a default. You weigh it against your required outgoing quality (DPPM target), the maturity of the process (a fresh node has more latent defects than a mature one), and the cost of an escape in the end application. Automotive and medical parts get burned in; a $3 consumer microcontroller on a mature node usually does not. The industry trend is to replace blanket burn-in where possible with smarter screens — stress only the parts statistics flag as suspect, or move stress to the wafer level — because 100% burn-in on a mature product is mostly money spent confirming parts you already knew were fine.

Adaptive Test and Part-Average Testing

A part can be inside every datasheet limit and still be a time bomb. A device whose leakage is 5x the lot median but still under the absolute max is technically good and statistically suspect — its abnormality is itself evidence of a latent defect. Outlier screening is the practice of failing parts not because they violate a fixed spec, but because they violate the behavior of their neighbors.

The canonical method is Part Average Testing (PAT), formalized by the Automotive Electronics Council as AEC-Q001. Instead of (or in addition to) the fixed datasheet limit, PAT computes statistical limits from the population — classically mean +/- 6 sigma (robust estimators in practice) — and fails parts outside that window even though they pass the absolute spec:

Static PAT limits (per parameter):
  PAT_upper = mean + N * sigma     (typ. N = 6, using robust median/IQR estimators)
  PAT_lower = mean - N * sigma

Dynamic PAT (DPAT): recompute mean/sigma per lot or per wafer,
so the limits track real process centering instead of a stale fixed number.

Geographic PAT (GPAT / spatial): fail a passing die because its
neighbors on the wafer failed — a good die in a bad cluster is suspect.

This generalizes into adaptive test: using data from one test step to change what happens at the next. Skip redundant tests on lots running clean; add tests or tighten limits on lots showing excursions; route suspect die to extra screens; feed wafer-sort results forward to bias final test. Adaptive test arose in the 2000s for automotive reliability and is now broadly used because it attacks both enemies at once — it removes outliers (quality) while letting clean material skip steps (cost). The trade-off is infrastructure: you need a data pipeline that can compute limits in near-real-time at the tester and a quality system that can defend why two identical-looking parts got different test treatments.

Guardbanding: Testing Tighter Than the Spec

If you promise a customer a part works at 3.0 GHz and you test it at exactly 3.0 GHz, you will ship failures. Every measurement has uncertainty — tester accuracy, calibration drift, temperature, site-to-site variation, the part’s own aging between test and use. Guardbanding is the deliberate practice of setting your test limits inside the datasheet limits by enough margin to absorb all of that uncertainty, so that a part you pass is genuinely good even in the customer’s worst case, not just on your tester on a good day.

Datasheet (customer) limit:        I_leak <= 100 uA
Test guardband for measurement
  uncertainty + drift + temp:      subtract 15 uA
Internal test limit (what ATE
  actually enforces):              I_leak <= 85 uA

A part at 90 uA is "good" per datasheet but FAILS your guarded test.
You overkill it on purpose. The alternative is shipping a part that
reads 90 uA on your tester and 105 uA on the customer's.

Guardbanding is the conscious decision to trade yield for confidence. A tighter guardband fails more good parts (overkill, lost yield); a looser one risks escapes (underkill, lost reputation). The right number comes from a measurement-system analysis: characterize your tester’s reproducibility, add the part’s worst-case drift, and set the band so the probability of an escape meets your quality target. It is the same philosophy as a read-window budget in flash, where margins are deliberately reserved against future drift rather than spent at time zero. And it interacts with PAT: guardbands handle known uncertainty with a fixed margin, while PAT handles statistical outliers that no fixed margin would catch.

What a DPPM Target Actually Commits You To

DPPM — defective parts per million — is the unit in which outgoing quality is contracted. It is exactly what it says: of every million parts you ship, how many are defective.

DPPM = (defective_parts_shipped / total_parts_shipped) * 1,000,000

  100 DPPM  = 1 bad part in 10,000      (consumer-ish)
   10 DPPM  = 1 bad part in 100,000     (high-rel commercial)
    1 DPPM  = 1 bad part in 1,000,000   (automotive-grade)
  "zero defects" = sub-1 DPPM, the AEC aspiration

Those small numbers commit a producer to an enormous amount. Consider the scale: a vendor shipping 1 billion parts a year at a 10 DPPM target is contracting to let no more than 10,000 defective parts escape in a year — and to be able to prove it statistically. That commitment cascades through every decision in this post:

It sets your test coverage. To catch defects at the parts-per-million level, your fault coverage (stuck-at, transition-delay, cell-level for memory) has to be high enough that the uncovered fraction times the unscreened defect density lands below your DPPM budget. Coverage gaps that were invisible at 1000 DPPM dominate at 1 DPPM.
It decides whether you burn in. If your post-final-test infant-mortality rate exceeds the DPPM target, burn-in (or a statistical equivalent) is not optional.
It forces adaptive screening. Fixed limits leave outliers in the population; hitting low single-digit DPPM essentially requires PAT/DPAT outlier removal because the last defects are statistical, not categorical.
It tightens guardbands. Lower DPPM means less tolerance for measurement escapes, which means more conservative test limits, which means lower yield. DPPM and yield trade against each other through the guardband.
It demands traceability. Meeting a DPPM contract means part-level genealogy: which wafer, which site, which tester, which program revision — so when a defect does escape, you can trace it from RMA to root cause and bound the rest of the population.

A DPPM number on a quote looks like marketing. It is actually a budget that has already decided how many test insertions you run, how tight your guardbands are, whether you own a burn-in floor, and how much yield you are willing to throw away to keep your escapes below a line you have signed your name to.

Verdict

Test is the step where silicon stops being physics and starts being a product. The newcomer’s mental model — “test checks if the chip works” — is true and almost useless; the working model is that test is a continuous optimization against two costs that never stop pulling apart. On one side, tester time is bill-of-materials: every second at four-and-a-half cents, divided by however many sites you can run in parallel, charged to every unit forever. On the other, every escape is a liability: a return, a recall, a DPPM contract violated. The whole apparatus — sort then final test to scrap cheaply, probe cards to make contact at all, KGD to keep stacked-die economics from collapsing, burn-in to drag infant mortality forward, PAT and adaptive test to fail the statistically suspect, guardbands to test tighter than you promise — exists to find the optimum between those two costs at the DPPM level your customer is paying for.

If you are about to own a test program, build these instincts: know your tester rate to the cent and treat test time like a budget line; understand that your probe card is a yield variable, not a fixture; never confuse “passes the datasheet” with “good,” because PAT and guardbanding both live in the gap between them; and read every DPPM target as the set of commitments it silently contains. A fab that yields well and tests badly ships defects; a fab that tests well and ignores the clock ships parts nobody can afford. The job is both, at once, on every die.