Failure Analysis: From RMA to Root Cause

June 12, 2026 18 min read The Physics of Computing

failure-analysissemiconductorsroot-causesemfibreliability

Contents

A return is a hypothesis you have not tested yet. A customer ships back a part and writes “dead on arrival” or “intermittent reset under load,” and that sentence is a claim about physics you cannot see. Failure analysis is the discipline of converting that claim into a coordinate on a die, a mechanism with a name, and a change to a process that stops the next one from coming back. It is debugging, but the bug lives in silicon, mold compound, and solder, and the print statements are photons, heat, and electron-scattering contrast. The reason FA is hard is the same reason it is interesting: every good technique trades information for the integrity of the sample, and the most informative techniques are the ones that destroy the part. So FA is structured around a single inviolable rule. You spend non-destructive observation first, you localize before you cut, and you do not pour acid on your only piece of evidence until you have squeezed every photon and every milliamp of signal out of it intact.

This post walks the full chain from RMA bin to corrective action, the way an FA engineer actually runs it. If you have read debugging strategies, the mental model transfers cleanly: reproduce, localize, isolate, root-cause, fix, and prevent regression. The vocabulary is just colder and the undo button does not exist.

The RMA is a bug report, and most bug reports are wrong

The first thing an experienced analyst distrusts is the failure description. “No power” frequently means a bent BGA ball or a board-level short, not a dead die. “Random crashes” is sometimes marginal timing that only manifests at a corner the customer’s bench happened to hit. So the FA flow opens the same way good software debugging opens: confirm the failure is real and reproducible before you spend a dime localizing it.

That confirmation step is electrical verification. You put the part on a curve tracer or a source-measure unit (SMU) and sweep each pin against ground and against the supply rails, watching the current-voltage (I-V) signature. A healthy input pin shows the textbook back-to-back ESD diode clamp: high impedance in the operating window, sharp conduction past the rail and below ground. A pin that has taken electrostatic discharge or electrical overstress reads differently even when there is no external mark. ESD damage often shows up as a soft leakage path that bleaks a few microamps where it should block, and electrical overstress (EOS) shows up as a hard short with a near-resistive I-V slope where a diode should be. Curve tracing is cheap, fast, and completely non-destructive, which is exactly why it goes first.

pin I-V signatures on the curve tracer (schematic)

  I |        healthy            I |   ESD leak           I |   EOS short
    |          /                  |        /               |     /
    |         /                   |      /                 |    /
 ---+--------+----  V          ---+----+/----- V        ---+---/------ V
    |       /|                    |  _/                    |  /
    |      / |                    | /  (soft, ~uA)         | /  (hard, ohmic)
    |     /  | clamp at rail      |/                       |/

If the part passes every electrical check, you have a different and harder problem: an intermittent or marginal failure that may need temperature, voltage, or pattern stress to reproduce. This is where FA borrows directly from production test. The same automatic test pattern generation (ATPG) vectors used to screen the die at the factory, covered in how semiconductors are tested, become a diagnostic instrument. You run the failing pattern, capture which scan cells mismatched, and feed that failure log to scan diagnosis software. The tool back-solves the logic cone and hands you a short list of candidate nets and gates. That is fault isolation done in pattern space rather than physical space, and on a modern logic die with billions of transistors it is the only realistic way to point at the suspect.

Package before die: see inside without opening it

Before anyone reaches for acid, there is a tier of non-destructive imaging that looks straight through the package. These tools are precious because they tell you whether the defect is even on the die or sitting in the package, which decides the entire downstream plan.

Two-dimensional X-ray radiography and 3D X-ray computed tomography (CT) image the metal: bond wires, leadframe, solder balls, copper pillars, through-silicon vias. A cracked wire bond, a void in a solder joint, a non-wet BGA ball, a misaligned die-stack: X-ray finds all of these without removing a single milligram of mold compound. Scanning acoustic microscopy (SAM, or C-SAM) does the complementary job: it pulses ultrasound into the package and listens for echoes at material interfaces, which makes it exquisitely sensitive to delamination and voids, the air gaps that X-ray sees poorly. Delamination at the die-attach or along the leadframe is a classic moisture-and-thermal-cycling failure, and SAM is the standard screen for it.

For opens and shorts buried in advanced flip-chip and 2.5D/3D packages, the package-level fault isolation tool of choice is time-domain reflectometry, and specifically its terahertz implementation, electro-optical terahertz pulse reflectometry (EOTPR). You launch a fast electrical pulse down a trace and time the reflection from the impedance discontinuity at the fault. EOTPR pushes the spatial resolution of this idea to better than about 10 microns, good enough to call out which microbump or which TSV in a stack is open without grinding the package down to find it. The honest trade-off across this whole tier is resolution versus penetration: these tools see through packaging precisely because they use radiation that does not interact strongly with it, and that same weak interaction caps how small a defect they can resolve. They narrow the search; they rarely close the case.

Technique	What it reveals	Destructive?	Typical resolution
Curve tracing / SMU I-V	ESD/EOS, leakage, opens, shorts (per pin)	No	electrical, pin-level
Scan diagnosis (ATPG)	Candidate failing nets/gates in logic	No	logical, gate-level
2D/3D X-ray (CT)	Wire/solder/TSV opens, cracks, voids in metal	No	~0.5-5 um
Scanning acoustic (C-SAM)	Delamination, die-attach voids, cracks	No	~10-50 um
EOTPR / TDR	Package opens/shorts (which bump/TSV)	No	< 10 um
Emission microscopy (EMMI)	Light-emitting defects: leakage, junctions	No	optical, ~0.5 um
Lock-in thermography (LIT)	Resistive/short hot spots (x, y, depth)	No	~5-10 um
OBIRCH / TIVA (laser stim)	Resistance/voltage anomalies, leakage paths	No	sub-micron
Decapsulation (acid/laser)	Exposes die for optical/EMMI/deprocess	Yes	n/a (gateway step)
FIB cross-section	Layer-by-layer structure at a site	Yes	nm-scale
SEM imaging	Surface/cross-section morphology	Mostly*	~1-10 nm
TEM (FIB lamella)	Atomic-scale defects, oxide thickness	Yes	< 1 nm

*SEM imaging is non-destructive in principle, but in practice the sample usually had to be deprocessed to get there.

Localization: making the defect light up

Once you suspect the die, you need a physical coordinate. This is the heart of FA and the place where the cleverest physics lives, because you are trying to make an invisible defect announce its own location. The two workhorses are emission microscopy and laser stimulation, and the beautiful thing is that both can work through the back side of the silicon, so you do not have to expose the front of the die to use them.

Emission microscopy (EMMI, sometimes PEM for photon emission microscopy) exploits the fact that defects emit light. A leaky junction, a transistor stuck in saturation, a gate-oxide pinhole conducting where it should not, a forward-biased parasitic, all of these emit faint photons through mechanisms like hot-carrier recombination and band-to-band emission. You bias the part to recreate the failure, cool a sensitive infrared-capable camera, integrate for seconds to minutes in a light-tight chamber, and overlay the emission spots on a CAD layout of the die. A bright spot where no spot belongs is your defect, located to roughly optical resolution. Silicon is transparent in the near-infrared, which is why backside EMMI works on flip-chip parts where the active circuitry faces the substrate and the front is inaccessible.

Lock-in thermography (LIT) attacks resistive defects, the shorts and high-resistance paths that dissipate heat. You drive the device with a periodic electrical excitation, a pulsed signal at a known frequency, and watch the surface with a thermal camera while a lock-in algorithm correlates the temperature signal to the excitation phase. Because it locks to the drive frequency, LIT digs a hot spot of a few millikelvin out of a noisy thermal background, and because heat takes time to diffuse to the surface, the phase delay encodes depth. That makes LIT one of the few tools that localizes a buried short in x, y, and z, which is invaluable in stacked and packaged parts. It is the standard tool for the low-ohmic short that does not emit light.

The laser-stimulation family, OBIRCH (optical beam-induced resistance change), TIVA (thermally-induced voltage alteration), and Seebeck effect imaging, scans a focused laser across the biased die and measures how the local heating perturbs the circuit’s current or voltage. A defect, a void in a via, a silicide anomaly, a leakage path, responds differently from healthy material, so the perturbation map paints the defect. These techniques are the go-to for ESD and EOS root-causing: published case studies show OBIRCH pinpointing the exact stressed transistors, later confirmed by physical deprocessing that found drain-to-source silicon melt right at the flagged sites. That confirmation step matters, and it is a theme worth stating plainly: localization gives you a hypothesis, not a verdict. You still have to go look.

Crossing the Rubicon: decapsulation

Everything so far has been reversible. Decapsulation is the first irreversible step, and you do not take it until the non-destructive tier has given you a target worth cutting to. There are two routes, and choosing between them is a real engineering decision with consequences for the evidence.

Chemical (wet) decap dissolves the epoxy mold compound with acid. The standard reagent for ordinary plastic packages is fuming nitric acid (HNO3), which attacks the epoxy aggressively while sparing gold bond wires and, mostly, the aluminum metallization on the die. Fuming sulfuric acid (oleum) is brought in for tougher inorganic-filled or glass-reinforced compounds that nitric alone will not touch. The catch is copper. Copper bond wires, now standard on cost-sensitive parts, corrode violently in nitric acid, so copper-wire devices need carefully tuned mixtures of red fuming nitric and sulfuric acid, often at sub-ambient temperature, to strip the epoxy without eating the very interconnect you are trying to inspect. Modern labs run automated jet-etchers (the Nisene JetEtch and Finetech-class tools) that dispense heated acid, 60 to 80 C, through a gasketed window over the die, control temperature and exposure precisely, and give reproducible results an operator dripping acid by hand cannot match, while keeping the chemist away from the fumes.

DECAP DECISION

  package type ----> reagent / method
  ------------       -----------------
  Au-wire plastic    fuming HNO3 (jet-etch, 60-80 C)
  Cu-wire plastic    HNO3/H2SO4 blend, sub-ambient
  glass/inorg fill   fuming H2SO4 (oleum)
  must preserve      LASER ablation to thin the cap,
   bonds/balls        then short chemical finish
  ceramic/lidded     mechanical delid (no chemistry)

Laser decap ablates the mold compound with focused pulses, opening a precise window over a chosen die region without dunking the whole part in acid. It is the method of choice when you must preserve fragile features, copper wires, or a specific area, and it is frequently combined with a brief chemical finish: the laser does the bulk removal, a gentle etch cleans up the last microns. The universal failure mode of this entire step is over-processing. Push the acid too long or too hot and you dissolve the aluminum metallization, lift the bonds, or stain the die surface, destroying the very defect you came to photograph. Decap is where FA most resembles archaeology: you are excavating evidence that you can ruin with one careless minute, and the discipline of stopping is as important as the technique of cutting.

Deprocessing and the imaging stack

A decapped die is a starting point, not an answer. To see a defect at the transistor or interconnect level you deprocess, removing the die layer by layer, metal then dielectric then metal, with wet chemistry, reactive-ion etching, or mechanical polish, and imaging at each plane. The goal is to arrive at the localized site with the failure exposed but not disturbed.

Optical microscopy comes first and still catches a surprising amount: corrosion, gross EOS craters, scratches, contamination, foreign material. When optical runs out of resolution, which on modern nodes is almost immediately, you move to the scanning electron microscope (SEM). SEM rasters a focused electron beam across the surface and forms an image from secondary and backscattered electrons, reaching nanometer-scale resolution with enormous depth of field. Voltage-contrast SEM is a particularly elegant trick: charged and uncharged nodes image at different brightness, so an open via or a floating gate literally shows up as the wrong shade of gray, turning an electrical fault into a visible one.

For the cross-section, the focused ion beam (FIB) is the precision scalpel. A FIB sputters material with a focused gallium-ion beam, milling a clean vertical trench exactly at the localized coordinate so you can see the layer stack in profile: a void in a tungsten via, a thinned barrier, a cracked dielectric, a contamination stringer bridging two lines. Dual-beam FIB-SEM instruments combine the ion column for milling and the electron column for imaging in one chamber, so you mill a slice, image it, mill deeper, image again, building up the three-dimensional structure of the defect. There are two costs to be honest about. Gallium ions implant into the top few nanometers of the cut face and amorphize it, so the surface you image is slightly altered by the act of imaging it. And on advanced logic, isolating one failing gate among billions can require so much careful FIB delayering and nanoprobing that a single cross-section consumes days of an expert’s time on a multi-million-dollar tool.

When the answer lives below even FIB-SEM resolution, gate-oxide thickness, an atomic-scale dislocation, the precise composition of a leaky interface, you use the FIB to cut a TEM lamella: a slice of die thinned to under about 90 nm, transparent to a transmission electron microscope. TEM resolves below a nanometer and, with energy-dispersive spectroscopy, tells you what the contamination is made of, not just that it is there. Reading these images is its own learned skill, closer to the structured pattern-matching of reverse engineering with Ghidra than to a measurement, you are reconstructing intent and mechanism from layout and morphology rather than running a number off a meter.

From defect to mechanism to corrective action

A photograph of a void is not a root cause. Root cause is a mechanism with a name and a cause you can act on, and getting there means connecting the physical evidence to a failure physics model. This is where FA reconnects to the reliability discipline. The mechanisms you are matching against, electromigration thinning a line, time-dependent dielectric breakdown punching through a gate oxide, stress-driven voiding, hot-carrier degradation shifting a threshold, moisture-driven corrosion, solder fatigue from thermal cycling, are exactly the ones characterized during qualification. The deep dive in NAND reliability physics and qualification lays out how these wear-out modes are modeled and accelerated, and FA is the inverse problem: given the post-mortem morphology, name the mechanism that produced it. A void in a via that grew preferentially in the electron-flow direction says electromigration. A pinhole in a gate oxide with a melt signature says dielectric breakdown. The morphology is a fingerprint, and matching it correctly is the difference between a real corrective action and a guess.

The structured frame for that last mile is the 8D process, the eight-discipline corrective-action method that originated in automotive quality and is now standard in semiconductor RMA flows. The FA techniques above feed it; they do not replace it.

RMA  ->  D1  team
          D2  describe the problem (the failure, precisely)
          D3  contain (quarantine suspect lots, stop the bleed)
          D4  ROOT CAUSE  <-- the FA chain lives here:
                 verify electrically (curve trace, scan diag)
                 localize (EMMI / LIT / OBIRCH)
                 deprocess (decap, FIB, SEM/TEM)
                 match morphology to failure mechanism
          D5  choose permanent corrective action
          D6  implement and validate it
          D7  prevent recurrence (update controls, specs,
                 screens, design rules; fix the escape point)
          D8  close and recognize; feed the lessons back

The discipline that earns FA its keep is D7’s escape point: not just why the part failed, but why the existing screens let it through. A defect that should have been caught by a burn-in step or an ATPG pattern but was not points to a hole in the test program, and closing that hole is often worth more than fixing the one returned part. This is the loop back to the fab. If FA traces a systematic defect to a particular layer or step, that finding flows into the corrective actions and design-of-experiments work described in semiconductor yield engineering, where a single confirmed root cause can lift the yield of every wafer that follows. One RMA, run all the way to ground, can pay for the lab.

It also helps to understand the device you are dissecting at the level of how a transistor actually works. An FA engineer who can read an emission spot as hot-carrier injection at a specific drain, or a leakage path as a punch-through under the gate, is reasoning about the same band diagrams and depletion regions that define the device’s intended operation. The defect is a deviation from that physics, and you cannot recognize the deviation if you do not know the baseline cold.

The honest trade-offs

FA is not magic, and pretending otherwise wastes money. Three trade-offs dominate every case.

The first is destructive ordering, the rule this whole post is built around. You get exactly one chance to image a defect in its as-failed state, so the sequence non-destructive, then destructive is not bureaucracy, it is the difference between an answer and a destroyed sample. The single most expensive mistake in the field is decapping or cross-sectioning before localization, because then you are cutting blind and you have spent your only evidence on a coin flip.

The second is cost and time versus depth. Curve tracing is minutes and cents. A TEM lamella is days and serious money, and the deeper you go the more you pay for diminishing returns. A good analyst stops at the shallowest technique that produces an actionable root cause, and resists the temptation to FIB everything because the picture would be pretty.

The third is reproducibility versus the intermittent failure. Many of the most painful field returns are marginal, timing-sensitive, temperature-sensitive, pattern-sensitive, and they simply will not emit, will not draw the leakage current, will not show the hot spot, unless you recreate the exact corner that triggered them. No imaging tool helps if you cannot bias the part into failing on the bench, which is why the unglamorous work of building a faithful reproduction case is often the hardest and most valuable part of the whole job. It is the same truth that haunts software debugging: the bug you cannot reproduce is the bug you cannot fix.

Verdict

Failure analysis is debugging with the undo button removed. The toolkit is deep, curve tracing and scan diagnosis to verify and pre-localize, X-ray, acoustic, and EOTPR to clear or implicate the package, emission microscopy, lock-in thermography, and laser stimulation to make the die-level defect announce itself, then decap, FIB, SEM, and TEM to expose and identify the mechanism, but the toolkit is not the discipline. The discipline is sequencing: spend every non-destructive observation before the first irreversible cut, localize before you deprocess, and treat the returned part as evidence you can only spend once. Plug that physical chain into the 8D loop, close the escape point as ruthlessly as the defect, and feed the confirmed root cause back to test and to the fab, and a single RMA stops being a cost center and becomes the most direct line you have from a failure in the field to a process that no longer produces it. The parts that come back are not failures of the product so much as questions the product is asking. FA is how you answer them in a language the fab can act on.