Chiplets and Advanced Packaging: When the Die Stopped Scaling

June 20, 2026 14 min read The Physics of Computing

chipletsadvanced-packagingsemiconductorscowosfoverosuciehardware

Contents

The most important number in modern processor design is not a transistor count or a clock speed. It is roughly 858 square millimeters — the reticle limit, the largest area a lithography scanner can expose in a single shot. For decades it did not matter, because nobody wanted a die that big and Moore’s Law made smaller transistors cheaper every couple of years. Both of those facts stopped being true at almost the same moment. AI accelerators wanted dies larger than the reticle, and the cost per transistor stopped falling as new nodes got exponentially more expensive to manufacture. The industry’s response was not a better transistor. It was to give up on the monolithic die entirely and start building processors the way you build a server rack: out of multiple smaller pieces, each chosen for its job, wired together by an interconnect. Those pieces are chiplets, the wiring is advanced packaging, and together they are the most consequential shift in how chips are physically built since the integrated circuit replaced discrete transistors. The interesting part is that this was driven almost entirely by economics, not physics — and economics, unlike physics, has exceptions.

Why the Monolithic Die Hit a Wall

A monolithic chip is one continuous piece of silicon: every core, every cache, every memory controller and I/O lane patterned onto a single die and cut from a single wafer. This is the simplest thing to design and the best-performing thing to run, because everything sits on the same substrate with the fastest, lowest-power on-die wires available. For most of computing history it was also the cheapest. Three things broke that.

First, the reticle limit. A scanner images a maximum field of about 26 mm × 33 mm. A design larger than that cannot be made as one piece, full stop. NVIDIA’s largest GPUs and the biggest AI training chips bumped into this ceiling, and you cannot negotiate with an optics constraint.

Second, yield collapses with area, which we will quantify in the next section. A defect that lands on a tiny die ruins a tiny die; the same defect on a giant die ruins a giant die. Bigger dies catch more defects and each loss is more expensive.

Third, and most importantly, node economics inverted. For thirty years a new process node delivered more transistors at lower cost per transistor, so you put everything on the newest node. But leading-edge nodes — 5 nm, 3 nm, and below — now cost so much per wafer, and yield so cautiously at first, that the cost-per-transistor curve flattened or reversed for some functions. Suddenly it made no sense to fabricate an I/O controller or an SRAM cache on a bleeding-edge node when those blocks do not benefit from it. The monolithic die forced everything onto the same node. That single constraint became the whole problem.

The Yield Math That Forces the Issue

The economic engine under chiplets is one equation. Defects land on a wafer roughly at random with some density D (defects per mm²). The probability a die of area A escapes every defect follows a Poisson-style model; a common refinement is Murphy’s model:

            ( 1 - e^(-A*D) )  2
   Yield =  ( -------------- )
            (     A*D        )

What matters is the shape, not the exact form: yield falls faster than linearly as die area grows. Split one big die into several small ones and the arithmetic changes dramatically. Consider a defect density of 0.1 defects/cm² and compare one 600 mm² monolithic die against four 150 mm² chiplets that do the same work:

Design	Die area	Approx. good-die yield	Effect
Monolithic	600 mm²	~55%	Every defect kills the whole chip
4 chiplets	150 mm² each	~85% each	A defect kills only one small tile

You then assemble the package from known-good dies — pieces individually tested before bonding — so the defective tiles never make it into a product. The yield improvement is not marginal; it can be the difference between a sellable product and an unsellable one for very large designs. This is the same logic our yield-engineering deep dive covers from the fab’s side, applied at the package level. AMD’s first Zen-based EPYC processors were the proof of concept: four small dies on one substrate yielded enormously better than the single huge die they would have required, and AMD could sell the parts that didn’t make the cut as lower-core-count SKUs instead of throwing them away.

The catch — and there is always a catch — is that the yield you win on silicon you partly give back on packaging. Bonding multiple dies precisely, adding interposers, and testing the assembled package all cost money and introduce their own defect modes. Chiplets win when the silicon yield savings exceed the packaging overhead, which is true for large dies and false for small ones.

2.5D, 3D, and the Vocabulary

“Advanced packaging” is a family of techniques, and the marketing names obscure a simple spectrum of how densely and how vertically you connect the dies. From cheapest and loosest to most expensive and tightest:

Organic substrate (2D). The dies sit side by side on a printed-circuit-like organic package and talk over traces in the substrate. Cheap, coarse, lower bandwidth. This is how mainstream AMD Ryzen and EPYC connect their compute dies to the I/O die.
Silicon interposer (2.5D). A passive slab of silicon under the dies carries thousands of fine wires and through-silicon vias (TSVs). Far denser than organic, which is why it is mandatory for parking High Bandwidth Memory (HBM) stacks next to a GPU. TSMC’s CoWoS is the archetype.
Silicon bridges (2.5D, localized). Instead of one big expensive interposer under everything, embed small silicon bridges only where two dies need dense connections. Intel’s EMIB does this — cheaper than a full interposer for designs that communicate in pairs rather than all-to-all.
3D stacking. Stack dies vertically and connect them face-to-face with TSVs or, increasingly, hybrid bonding (direct copper-to-copper bonds with no solder bumps, enabling thousands of connections per mm²). Intel Foveros and AMD’s 3D V-Cache do this. Highest density and shortest wires; hardest thermal problem because you are stacking heat sources.

A cross-section makes the spectrum concrete:

  2D (organic substrate)        2.5D (silicon interposer)
  +------+   +------+           +------+   +------+   +-----+
  | die  |   | die  |           | logic|   | logic|   | HBM |
  +--||--+   +--||--+           +--||--+   +--||--+   +--||-+
  ===organic substrate===       |  silicon interposer (TSVs) |
                                 ========organic substrate=====

  3D stacking (Foveros / hybrid bonding)
        +-----------------+
        |  compute die    |   <- top die (hot)
        |~~hybrid bond~~~~~|   <- Cu-Cu, TSVs
        |  base/cache die |
        +-----------------+
        ===organic substrate===

The whole game is buying interconnect density. On-die wires are essentially free in power and latency; the moment a signal has to leave a die and cross to another, it costs picojoules per bit and nanoseconds of latency. Each step up this ladder — organic to interposer to bridge to 3D bond — narrows that penalty by packing the inter-die wires closer together and making them shorter, at escalating manufacturing cost.

The Players and Their Packaging

Every major silicon vendor has picked a different point on that spectrum, tuned to what they build. The names are proprietary; the underlying techniques are the ones above.

Vendor	Technology	Type	Where it shows up
AMD	Infinity Fabric (on organic substrate)	2D / die-to-die protocol	Ryzen, EPYC: compute dies + I/O die
AMD	3D V-Cache (TSMC SoIC hybrid bonding)	3D stack	X3D desktop CPUs, MI300
Intel	EMIB	2.5D embedded bridge	Sapphire Rapids, Ponte Vecchio
Intel	Foveros	3D stacking	Meteor Lake, Arrow Lake tiles
Apple	UltraFusion	2.5D bridge/interposer	M-series Ultra (two Max dies joined)
TSMC	CoWoS (S/R/L variants)	2.5D interposer	NVIDIA datacenter GPUs + HBM

AMD’s Infinity Fabric is both a physical link and a coherent protocol; on desktop and server parts the compute “core complex dies” (CCDs) sit beside a central I/O die on a plain organic substrate, which keeps cost low and is why AMD could ship 64-core server chips years before a monolithic equivalent was feasible. Intel splits the difference: EMIB embeds small silicon bridges in the substrate for 2.5D side-by-side connections, while Foveros stacks tiles vertically — Meteor Lake and Arrow Lake client CPUs use Foveros to stack separate compute, graphics, SoC, and I/O tiles, each potentially on a different node. Apple’s UltraFusion fuses two Max-class dies into an Ultra with a dense die-to-die bridge carrying over 10,000 signals and multiple terabytes per second of bandwidth, presenting the result to software as a single chip. And TSMC’s CoWoS is the workhorse of the AI boom: a silicon interposer that lets a logic die sit shoulder to shoulder with stacks of HBM, which is the only practical way to feed a datacenter GPU the memory bandwidth it needs. The CoWoS-L variant, using local silicon interconnect bridges inside the interposer, is what NVIDIA’s largest training GPUs are built on, and interposers have grown to several times the reticle size to fit ever-bigger logic plus eight HBM stacks.

Heterogeneous Integration: Mixing Nodes

The yield argument got chiplets in the door, but the durable economic win is heterogeneous integration — putting each function on the node that suits it instead of dragging everything onto the leading edge. This directly attacks the node-cost problem that motivated the whole shift.

Consider what is actually on a modern server processor. The cores want the densest, fastest, most expensive node — 3 nm, say — because logic genuinely benefits from it. But the memory controllers, PCIe and I/O logic, and large SRAM caches do not scale well on new nodes (SRAM in particular has nearly stopped shrinking) and gain little from them. On a monolithic die, all of it pays the 3 nm wafer price. With chiplets, you fabricate the compute dies on 3 nm and the I/O die on a mature, cheap, high-yielding node like 6 nm or 12 nm, then bond them together. AMD has done exactly this since Zen 2: leading-node CCDs paired with an I/O die on an older, cheaper process. You get leading-edge compute and mature-node economics in the same package — something a single die physically cannot do.

The same principle explains HBM next to a GPU. The memory is built and stacked by a memory vendor on a memory-optimized process; the logic is built by a logic foundry on a logic process; the interposer marries them. Trying to integrate that much DRAM onto a logic die would be technically absurd and economically ruinous. Heterogeneous integration also enables reuse: the identical compute chiplet can populate a desktop part, a workstation part, and a 96-core server part, amortizing one expensive design across an entire product stack. The chiplet becomes a Lego brick, and the package is where you decide which product to build.

UCIe and the Open Chiplet Dream

So far every chiplet system is a single vendor connecting its own dies with its own proprietary link. The ambitious vision is a marketplace: standardized die-to-die interfaces so you could buy a compute chiplet from one company, an I/O chiplet from another, an accelerator from a third, and bond them into a custom package the way you assemble a PCB from catalog parts. The leading standard for this is UCIe (Universal Chiplet Interconnect Express), launched in 2022 and backed by essentially the entire industry — Intel, AMD, Arm, TSMC, Samsung, and others. It defines the physical layer, the protocol, and the packaging assumptions for chiplets to interoperate, much as PCIe standardized board-level expansion.

The dream is real but the friction is enormous. A die-to-die link is not a clean board connector; it is thousands of micro-bumps with tight electrical, thermal, and mechanical tolerances, and known-good-die testing, warranty, and integration responsibility get genuinely hard when chiplets come from different vendors. Whose fault is a failure in a multi-vendor package? Who guarantees the dies were good before assembly? For now, UCIe mostly standardizes the interface within a company’s own designs and for tightly negotiated partnerships, with the open mix-and-match bazaar still more roadmap than reality. It is the right direction and it will take years. The lesson from PCIe and other interconnect standards is that the ecosystem follows the standard slowly, then all at once.

Where Chiplets Pay Off, And Where They Don’t

The honest engineering reality is that chiplets are a trade, not a free win, and the trade only clears for certain products. Splitting a die imposes real costs that a monolithic design simply does not pay:

Power. Driving a signal off-die and across an interconnect costs meaningfully more energy per bit than an on-die wire. For a battery-powered phone, that inter-die tax is unacceptable, which is why flagship mobile SoCs remain stubbornly monolithic.
Latency and NUMA. When cores on one die need data attached to another die, the cross-die hop adds latency and creates non-uniform memory access effects that software and schedulers must account for. The first chiplet EPYCs had real memory-latency quirks because of this.
Thermal. 3D stacking puts heat sources on top of each other, and the die in the middle of a stack is the hardest thing in computing to cool. This caps how aggressively you can stack the hottest logic.
Packaging cost and complexity. Interposers, bridges, hybrid bonding, and the extra test steps all add cost and yield risk of their own. Below a certain die size, that overhead exceeds the silicon-yield savings.

So the rule of thumb falls out cleanly. Chiplets win for big things: server CPUs with dozens of cores, datacenter GPUs that exceed the reticle, AI accelerators that need HBM bandwidth — anywhere the die is large enough that monolithic yield is poor and the package overhead is small in relative terms. Monolithic wins for small things: phone SoCs, microcontrollers, and modest client chips, where the die already yields well, latency and power budgets are tight, and the packaging tax would dominate. The most interesting middle ground is client PC CPUs, where Intel’s Meteor Lake bet that the flexibility of tiles is worth the power overhead and AMD continues to mix monolithic mobile parts with chiplet desktop parts depending on the segment. There is no universal answer, only a break-even point that each product crosses or doesn’t.

Verdict

Chiplets are what an industry does when transistor scaling stops paying the bills but demand for compute keeps climbing. They did not make any single transistor faster; they changed the unit of construction from the die to the package, and in doing so unlocked three things a monolithic die could not deliver: products larger than the reticle, dramatically better yield on big designs, and the freedom to build each function on the node that actually suits it. That last point — heterogeneous integration — is the one that will outlast the current AI gold rush, because it permanently decouples “what node is best for compute” from “what node is best for cache and I/O,” and that decoupling is worth real money on every large chip.

But the honest framing is that advanced packaging is a cost-optimization and scaling workaround, not a performance miracle, and it carries a tax in power, latency, thermals, and packaging complexity that makes it the wrong choice for everything small. The future is not “everything becomes chiplets.” It is a bifurcation: the big, expensive, reticle-straining silicon at the top of the market goes multi-die and increasingly 3D-stacked, while the high-volume small stuff stays monolithic because the package overhead never clears the bar. If UCIe and open die-to-die standards eventually mature into a real marketplace, the design of a processor could start to look like the design of a system — picking parts from a catalog and wiring them together — which would be the most significant change to how chips are architected in fifty years. For now, the die stopped scaling, the package picked up the slack, and the most advanced silicon on earth is held together with bridges, interposers, and copper bonds finer than a wavelength of light.