Why planar NAND hit a wall at 15nm, how the industry turned the bit line vertical, charge-trap versus floating-gate cells, string stacking, the channel-hole etch that gates everything, CMOS under and bonded to the array, and what the 300-layer class actually means.
Nand-Flash
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3D NAND Architecture: Building Memory Sideways, Then Up -
NAND Trim: Calibrating Flash Memory at the Factory Every NAND die leaves the fab analog and imperfect. Trim is the layer of per-die calibration constants — read levels, program voltages, pump regulation, timing — that makes billions of slightly different devices behave like one uniform product. From first principles to what managing trim settings actually involves.
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QLC, PLC, and the Density Endgame Each extra bit per cell doubles the voltage states crammed into the same window: the exponential-pain, linear-gain math of multi-level NAND, where QLC genuinely works versus where it's a trap, SLC caching as the universal apology, and an honest read on whether PLC ever ships.
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The Read Window Budget: Margin Accounting in NAND Design Every NAND reliability mechanism — retention loss, read disturb, cycling wear, temperature shift — is a withdrawal from one shared account: the read window budget. How the budget is defined, measured, allocated, and defended, and why every flash failure story is ultimately a budget overrun.
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What Comes After NAND? Every "NAND killer" so far has died instead: the 3D XPoint post-mortem, honest assessments of MRAM, ReRAM, FeRAM, and PCM, why incumbency in memory is nearly unbeatable, and where the post-NAND future actually lives — bonded silicon, CXL tiers, and NAND replacing NAND.