Compute Express Link is the memory tier 3D XPoint died chasing — rebuilt from commodity DRAM over a cache-coherent link on the PCIe physical layer. How CXL.io/.cache/.mem work, the Type 1/2/3 device taxonomy, the 1.1-to-3.0 progression from expansion to pooling to true sharing, the real latency tax, and how Linux actually tiers it.
Pcie
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CXL: Memory Pooling and the Disaggregated Server -
Thunderbolt and USB4: How Tunneling Actually Works The single most important idea in modern connectivity is that the cable stopped carrying one protocol and started carrying a switchable fabric. How USB4 and Thunderbolt tunnel PCIe, DisplayPort, and USB3 over the same wire, the router-and-adapter architecture underneath, PAM3 and the 120Gbps asymmetric trick, the DMA security problem, and why the USB-C port is a lie.
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PCIe for Systems Engineers PCIe for people who currently stop at `lspci` — lanes, generations, bifurcation, and IOMMU explained well enough to diagnose a GPU training at half speed or an NVMe drive hitting a third of its rated IOPS from `lspci -vvv` output.