Raw NAND ships with thousands of bit errors per page and would be unusable without error correction. This is the story of how ECC evolved from single-bit Hamming through BCH to soft-decision LDPC, what "soft bits" physically are, and the UBER math that turns a noisy die into a reliability promise.
Nand
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ECC for Flash: Hamming to LDPC -
NAND Interfaces: ONFI, Toggle, and the Speed Problem The wire between the flash die and the controller has quietly become the thing that bounds SSD throughput. A tour of ONFI and Toggle Mode, the climb from asynchronous SDR to 3600 MT/s NV-DDR3, what read/write training actually does, and why signal integrity now dictates how many dies you can hang off a channel.
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NAND Reliability Physics and Qual NAND reliability is one trade governed by oxide physics: every electron you force through the tunnel oxide to write data also damages the oxide that has to hold it. This post builds from trap generation and SILC up to JESD218, JESD219, and the AEC-Q100 automotive delta, and teaches you to read an endurance/retention spec like a qual engineer.
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The Flash Translation Layer The FTL is the firmware lie that lets your SSD pretend to be a disk. A tour of L2P mapping, garbage collection and the write-amplification math, why overprovisioning is the master knob, how wear leveling and TRIM fit, and why fresh-out-of-box benchmarks are marketing and steady state is the only truth.
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The NAND Commodity Cycle Why NAND flash is a commodity whose price crashes and spikes with terrifying violence: the multi-year capex lead times, fixed-cost economics, and brutal consolidation down to five players that turn storage into a boom-bust market where the cycle, not the engineering, decides who lives and who dies.