Compute Express Link is the memory tier 3D XPoint died chasing — rebuilt from commodity DRAM over a cache-coherent link on the PCIe physical layer. How CXL.io/.cache/.mem work, the Type 1/2/3 device taxonomy, the 1.1-to-3.0 progression from expansion to pooling to true sharing, the real latency tax, and how Linux actually tiers it.
Memory
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CXL: Memory Pooling and the Disaggregated Server -
DDR5 and Why Memory Latency Stopped Improving DRAM capacity grew 128x and bandwidth 20x in two decades while latency barely moved 1.3x. Why the time to fetch the first byte has been stuck near 13 nanoseconds since DDR3, what DDR5 actually changed — dual sub-channels, more bank groups, on-die ECC, the PMIC — and why every one of those wins is about bandwidth and reliability, not the latency wall it cannot break.
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Linux Memory Management Deep Dive A comprehensive guide to Linux virtual memory, huge pages, NUMA topology, OOM killer tuning, /proc/meminfo interpretation, and using perf mem to find memory bottlenecks.