DRAM capacity grew 128x and bandwidth 20x in two decades while latency barely moved 1.3x. Why the time to fetch the first byte has been stuck near 13 nanoseconds since DDR3, what DDR5 actually changed — dual sub-channels, more bank groups, on-die ECC, the PMIC — and why every one of those wins is about bandwidth and reliability, not the latency wall it cannot break.
Dram
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DDR5 and Why Memory Latency Stopped Improving